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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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5bafeb6e7e
The 88E6141/6341 switches (also known as Topaz) have 1 SGMII lane, which can be configured the same way as the SERDES lane on 88E6390. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: David S. Miller <davem@davemloft.net>
349 lines
8.1 KiB
C
349 lines
8.1 KiB
C
/*
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* Marvell 88E6xxx SERDES manipulation, via SMI bus
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2017 Andrew Lunn <andrew@lunn.ch>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/mii.h>
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#include "chip.h"
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#include "global2.h"
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#include "phy.h"
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#include "port.h"
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#include "serdes.h"
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static int mv88e6352_serdes_read(struct mv88e6xxx_chip *chip, int reg,
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u16 *val)
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{
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return mv88e6xxx_phy_page_read(chip, MV88E6352_ADDR_SERDES,
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MV88E6352_SERDES_PAGE_FIBER,
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reg, val);
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}
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static int mv88e6352_serdes_write(struct mv88e6xxx_chip *chip, int reg,
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u16 val)
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{
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return mv88e6xxx_phy_page_write(chip, MV88E6352_ADDR_SERDES,
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MV88E6352_SERDES_PAGE_FIBER,
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reg, val);
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}
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static int mv88e6352_serdes_power_set(struct mv88e6xxx_chip *chip, bool on)
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{
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u16 val, new_val;
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int err;
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err = mv88e6352_serdes_read(chip, MII_BMCR, &val);
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if (err)
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return err;
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if (on)
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new_val = val & ~BMCR_PDOWN;
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else
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new_val = val | BMCR_PDOWN;
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if (val != new_val)
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err = mv88e6352_serdes_write(chip, MII_BMCR, new_val);
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return err;
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}
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static bool mv88e6352_port_has_serdes(struct mv88e6xxx_chip *chip, int port)
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{
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u8 cmode;
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int err;
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err = mv88e6xxx_port_get_cmode(chip, port, &cmode);
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if (err) {
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dev_err(chip->dev, "failed to read cmode\n");
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return false;
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}
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if ((cmode == MV88E6XXX_PORT_STS_CMODE_100BASE_X) ||
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(cmode == MV88E6XXX_PORT_STS_CMODE_1000BASE_X) ||
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(cmode == MV88E6XXX_PORT_STS_CMODE_SGMII))
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return true;
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return false;
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}
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int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, bool on)
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{
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int err;
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if (mv88e6352_port_has_serdes(chip, port)) {
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err = mv88e6352_serdes_power_set(chip, on);
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if (err < 0)
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return err;
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}
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return 0;
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}
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struct mv88e6352_serdes_hw_stat {
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char string[ETH_GSTRING_LEN];
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int sizeof_stat;
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int reg;
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};
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static struct mv88e6352_serdes_hw_stat mv88e6352_serdes_hw_stats[] = {
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{ "serdes_fibre_rx_error", 16, 21 },
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{ "serdes_PRBS_error", 32, 24 },
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};
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int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port)
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{
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if (mv88e6352_port_has_serdes(chip, port))
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return ARRAY_SIZE(mv88e6352_serdes_hw_stats);
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return 0;
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}
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int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip,
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int port, uint8_t *data)
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{
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struct mv88e6352_serdes_hw_stat *stat;
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int i;
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if (!mv88e6352_port_has_serdes(chip, port))
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return 0;
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for (i = 0; i < ARRAY_SIZE(mv88e6352_serdes_hw_stats); i++) {
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stat = &mv88e6352_serdes_hw_stats[i];
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memcpy(data + i * ETH_GSTRING_LEN, stat->string,
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ETH_GSTRING_LEN);
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}
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return ARRAY_SIZE(mv88e6352_serdes_hw_stats);
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}
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static uint64_t mv88e6352_serdes_get_stat(struct mv88e6xxx_chip *chip,
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struct mv88e6352_serdes_hw_stat *stat)
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{
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u64 val = 0;
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u16 reg;
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int err;
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err = mv88e6352_serdes_read(chip, stat->reg, ®);
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if (err) {
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dev_err(chip->dev, "failed to read statistic\n");
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return 0;
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}
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val = reg;
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if (stat->sizeof_stat == 32) {
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err = mv88e6352_serdes_read(chip, stat->reg + 1, ®);
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if (err) {
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dev_err(chip->dev, "failed to read statistic\n");
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return 0;
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}
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val = val << 16 | reg;
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}
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return val;
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}
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int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
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uint64_t *data)
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{
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struct mv88e6xxx_port *mv88e6xxx_port = &chip->ports[port];
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struct mv88e6352_serdes_hw_stat *stat;
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u64 value;
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int i;
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if (!mv88e6352_port_has_serdes(chip, port))
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return 0;
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BUILD_BUG_ON(ARRAY_SIZE(mv88e6352_serdes_hw_stats) >
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ARRAY_SIZE(mv88e6xxx_port->serdes_stats));
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for (i = 0; i < ARRAY_SIZE(mv88e6352_serdes_hw_stats); i++) {
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stat = &mv88e6352_serdes_hw_stats[i];
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value = mv88e6352_serdes_get_stat(chip, stat);
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mv88e6xxx_port->serdes_stats[i] += value;
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data[i] = mv88e6xxx_port->serdes_stats[i];
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}
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return ARRAY_SIZE(mv88e6352_serdes_hw_stats);
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}
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/* Set the power on/off for 10GBASE-R and 10GBASE-X4/X2 */
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static int mv88e6390_serdes_10g(struct mv88e6xxx_chip *chip, int addr, bool on)
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{
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u16 val, new_val;
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int reg_c45;
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int err;
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reg_c45 = MII_ADDR_C45 | MV88E6390_SERDES_DEVICE |
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MV88E6390_PCS_CONTROL_1;
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err = mv88e6xxx_phy_read(chip, addr, reg_c45, &val);
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if (err)
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return err;
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if (on)
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new_val = val & ~(MV88E6390_PCS_CONTROL_1_RESET |
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MV88E6390_PCS_CONTROL_1_LOOPBACK |
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MV88E6390_PCS_CONTROL_1_PDOWN);
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else
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new_val = val | MV88E6390_PCS_CONTROL_1_PDOWN;
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if (val != new_val)
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err = mv88e6xxx_phy_write(chip, addr, reg_c45, new_val);
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return err;
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}
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/* Set the power on/off for 10GBASE-R and 10GBASE-X4/X2 */
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static int mv88e6390_serdes_sgmii(struct mv88e6xxx_chip *chip, int addr,
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bool on)
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{
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u16 val, new_val;
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int reg_c45;
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int err;
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reg_c45 = MII_ADDR_C45 | MV88E6390_SERDES_DEVICE |
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MV88E6390_SGMII_CONTROL;
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err = mv88e6xxx_phy_read(chip, addr, reg_c45, &val);
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if (err)
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return err;
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if (on)
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new_val = val & ~(MV88E6390_SGMII_CONTROL_RESET |
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MV88E6390_SGMII_CONTROL_LOOPBACK |
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MV88E6390_SGMII_CONTROL_PDOWN);
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else
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new_val = val | MV88E6390_SGMII_CONTROL_PDOWN;
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if (val != new_val)
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err = mv88e6xxx_phy_write(chip, addr, reg_c45, new_val);
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return err;
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}
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static int mv88e6390_serdes_lower(struct mv88e6xxx_chip *chip, u8 cmode,
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int port_donor, int lane, bool rxaui, bool on)
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{
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int err;
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u8 cmode_donor;
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err = mv88e6xxx_port_get_cmode(chip, port_donor, &cmode_donor);
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if (err)
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return err;
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switch (cmode_donor) {
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case MV88E6XXX_PORT_STS_CMODE_RXAUI:
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if (!rxaui)
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break;
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/* Fall through */
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case MV88E6XXX_PORT_STS_CMODE_1000BASE_X:
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case MV88E6XXX_PORT_STS_CMODE_SGMII:
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case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
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if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASE_X ||
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cmode == MV88E6XXX_PORT_STS_CMODE_SGMII)
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return mv88e6390_serdes_sgmii(chip, lane, on);
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}
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return 0;
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}
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static int mv88e6390_serdes_port9(struct mv88e6xxx_chip *chip, u8 cmode,
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bool on)
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{
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switch (cmode) {
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case MV88E6XXX_PORT_STS_CMODE_1000BASE_X:
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case MV88E6XXX_PORT_STS_CMODE_SGMII:
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return mv88e6390_serdes_sgmii(chip, MV88E6390_PORT9_LANE0, on);
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case MV88E6XXX_PORT_STS_CMODE_XAUI:
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case MV88E6XXX_PORT_STS_CMODE_RXAUI:
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case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
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return mv88e6390_serdes_10g(chip, MV88E6390_PORT9_LANE0, on);
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}
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return 0;
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}
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static int mv88e6390_serdes_port10(struct mv88e6xxx_chip *chip, u8 cmode,
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bool on)
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{
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switch (cmode) {
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case MV88E6XXX_PORT_STS_CMODE_SGMII:
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return mv88e6390_serdes_sgmii(chip, MV88E6390_PORT10_LANE0, on);
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case MV88E6XXX_PORT_STS_CMODE_XAUI:
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case MV88E6XXX_PORT_STS_CMODE_RXAUI:
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case MV88E6XXX_PORT_STS_CMODE_1000BASE_X:
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case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
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return mv88e6390_serdes_10g(chip, MV88E6390_PORT10_LANE0, on);
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}
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return 0;
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}
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int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, bool on)
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{
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u8 cmode;
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int err;
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err = mv88e6xxx_port_get_cmode(chip, port, &cmode);
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if (err)
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return err;
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switch (port) {
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case 2:
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return mv88e6390_serdes_lower(chip, cmode, 9,
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MV88E6390_PORT9_LANE1,
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false, on);
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case 3:
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return mv88e6390_serdes_lower(chip, cmode, 9,
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MV88E6390_PORT9_LANE2,
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true, on);
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case 4:
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return mv88e6390_serdes_lower(chip, cmode, 9,
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MV88E6390_PORT9_LANE3,
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true, on);
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case 5:
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return mv88e6390_serdes_lower(chip, cmode, 10,
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MV88E6390_PORT10_LANE1,
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false, on);
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case 6:
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return mv88e6390_serdes_lower(chip, cmode, 10,
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MV88E6390_PORT10_LANE2,
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true, on);
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case 7:
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return mv88e6390_serdes_lower(chip, cmode, 10,
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MV88E6390_PORT10_LANE3,
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true, on);
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case 9:
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return mv88e6390_serdes_port9(chip, cmode, on);
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case 10:
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return mv88e6390_serdes_port10(chip, cmode, on);
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}
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return 0;
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}
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int mv88e6341_serdes_power(struct mv88e6xxx_chip *chip, int port, bool on)
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{
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int err;
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u8 cmode;
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if (port != 5)
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return 0;
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err = mv88e6xxx_port_get_cmode(chip, port, &cmode);
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if (err)
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return err;
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if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASE_X ||
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cmode == MV88E6XXX_PORT_STS_CMODE_SGMII ||
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cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX)
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return mv88e6390_serdes_sgmii(chip, MV88E6341_ADDR_SERDES, on);
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return 0;
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}
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