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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a64e697cef
Base enablement patch to register performance monitoring hardware support for power10. Patch introduce the raw event encoding format, defines the supported list of events, config fields for the event attributes and their corresponding bit values which are exported via sysfs. Patch also enhances the support function in isa207_common.c to include power10 pmu hardware. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1594996707-3727-9-git-send-email-atrajeev@linux.vnet.ibm.com
71 lines
2.1 KiB
C
71 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Performance counter support for POWER10 processors.
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*
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* Copyright 2020 Madhavan Srinivasan, IBM Corporation.
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* Copyright 2020 Athira Rajeev, IBM Corporation.
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*/
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/*
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* Power10 event codes.
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*/
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EVENT(PM_RUN_CYC, 0x600f4);
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EVENT(PM_DISP_STALL_CYC, 0x100f8);
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EVENT(PM_EXEC_STALL, 0x30008);
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EVENT(PM_RUN_INST_CMPL, 0x500fa);
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EVENT(PM_BR_CMPL, 0x4d05e);
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EVENT(PM_BR_MPRED_CMPL, 0x400f6);
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/* All L1 D cache load references counted at finish, gated by reject */
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EVENT(PM_LD_REF_L1, 0x100fc);
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/* Load Missed L1 */
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EVENT(PM_LD_MISS_L1, 0x3e054);
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/* Store Missed L1 */
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EVENT(PM_ST_MISS_L1, 0x300f0);
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/* L1 cache data prefetches */
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EVENT(PM_LD_PREFETCH_CACHE_LINE_MISS, 0x1002c);
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/* Demand iCache Miss */
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EVENT(PM_L1_ICACHE_MISS, 0x200fc);
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/* Instruction fetches from L1 */
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EVENT(PM_INST_FROM_L1, 0x04080);
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/* Instruction Demand sectors wriittent into IL1 */
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EVENT(PM_INST_FROM_L1MISS, 0x03f00000001c040);
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/* Instruction prefetch written into IL1 */
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EVENT(PM_IC_PREF_REQ, 0x040a0);
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/* The data cache was reloaded from local core's L3 due to a demand load */
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EVENT(PM_DATA_FROM_L3, 0x01340000001c040);
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/* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
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EVENT(PM_DATA_FROM_L3MISS, 0x300fe);
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/* Data PTEG reload */
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EVENT(PM_DTLB_MISS, 0x300fc);
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/* ITLB Reloaded */
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EVENT(PM_ITLB_MISS, 0x400fc);
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EVENT(PM_RUN_CYC_ALT, 0x0001e);
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EVENT(PM_RUN_INST_CMPL_ALT, 0x00002);
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/*
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* Memory Access Events
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*
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* Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0)
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* To enable capturing of memory profiling, these MMCRA bits
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* needs to be programmed and corresponding raw event format
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* encoding.
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*
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* MMCRA bits encoding needed are
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* SM (Sampling Mode)
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* EM (Eligibility for Random Sampling)
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* TECE (Threshold Event Counter Event)
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* TS (Threshold Start Event)
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* TE (Threshold End Event)
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*
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* Corresponding Raw Encoding bits:
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* sample [EM,SM]
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* thresh_sel (TECE)
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* thresh start (TS)
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* thresh end (TE)
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*/
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EVENT(MEM_LOADS, 0x34340401e0);
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EVENT(MEM_STORES, 0x343c0401e0);
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