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a64e697cef
Base enablement patch to register performance monitoring hardware support for power10. Patch introduce the raw event encoding format, defines the supported list of events, config fields for the event attributes and their corresponding bit values which are exported via sysfs. Patch also enhances the support function in isa207_common.c to include power10 pmu hardware. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1594996707-3727-9-git-send-email-atrajeev@linux.vnet.ibm.com
261 lines
10 KiB
C
261 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2009 Paul Mackerras, IBM Corporation.
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* Copyright 2013 Michael Ellerman, IBM Corporation.
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* Copyright 2016 Madhavan Srinivasan, IBM Corporation.
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*/
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#ifndef _LINUX_POWERPC_PERF_ISA207_COMMON_H_
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#define _LINUX_POWERPC_PERF_ISA207_COMMON_H_
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#include <linux/kernel.h>
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#include <linux/perf_event.h>
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#include <asm/firmware.h>
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#include <asm/cputable.h>
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#define EVENT_EBB_MASK 1ull
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#define EVENT_EBB_SHIFT PERF_EVENT_CONFIG_EBB_SHIFT
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#define EVENT_BHRB_MASK 1ull
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#define EVENT_BHRB_SHIFT 62
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#define EVENT_WANTS_BHRB (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT)
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#define EVENT_IFM_MASK 3ull
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#define EVENT_IFM_SHIFT 60
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#define EVENT_THR_CMP_SHIFT 40 /* Threshold CMP value */
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#define EVENT_THR_CMP_MASK 0x3ff
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#define EVENT_THR_CTL_SHIFT 32 /* Threshold control value (start/stop) */
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#define EVENT_THR_CTL_MASK 0xffull
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#define EVENT_THR_SEL_SHIFT 29 /* Threshold select value */
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#define EVENT_THR_SEL_MASK 0x7
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#define EVENT_THRESH_SHIFT 29 /* All threshold bits */
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#define EVENT_THRESH_MASK 0x1fffffull
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#define EVENT_SAMPLE_SHIFT 24 /* Sampling mode & eligibility */
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#define EVENT_SAMPLE_MASK 0x1f
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#define EVENT_CACHE_SEL_SHIFT 20 /* L2/L3 cache select */
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#define EVENT_CACHE_SEL_MASK 0xf
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#define EVENT_IS_L1 (4 << EVENT_CACHE_SEL_SHIFT)
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#define EVENT_PMC_SHIFT 16 /* PMC number (1-based) */
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#define EVENT_PMC_MASK 0xf
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#define EVENT_UNIT_SHIFT 12 /* Unit */
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#define EVENT_UNIT_MASK 0xf
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#define EVENT_COMBINE_SHIFT 11 /* Combine bit */
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#define EVENT_COMBINE_MASK 0x1
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#define EVENT_COMBINE(v) (((v) >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK)
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#define EVENT_MARKED_SHIFT 8 /* Marked bit */
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#define EVENT_MARKED_MASK 0x1
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#define EVENT_IS_MARKED (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT)
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#define EVENT_PSEL_MASK 0xff /* PMCxSEL value */
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/* Bits defined by Linux */
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#define EVENT_LINUX_MASK \
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((EVENT_EBB_MASK << EVENT_EBB_SHIFT) | \
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(EVENT_BHRB_MASK << EVENT_BHRB_SHIFT) | \
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(EVENT_IFM_MASK << EVENT_IFM_SHIFT))
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#define EVENT_VALID_MASK \
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((EVENT_THRESH_MASK << EVENT_THRESH_SHIFT) | \
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(EVENT_SAMPLE_MASK << EVENT_SAMPLE_SHIFT) | \
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(EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT) | \
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(EVENT_PMC_MASK << EVENT_PMC_SHIFT) | \
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(EVENT_UNIT_MASK << EVENT_UNIT_SHIFT) | \
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(EVENT_COMBINE_MASK << EVENT_COMBINE_SHIFT) | \
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(EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \
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EVENT_LINUX_MASK | \
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EVENT_PSEL_MASK)
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#define ONLY_PLM \
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(PERF_SAMPLE_BRANCH_USER |\
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PERF_SAMPLE_BRANCH_KERNEL |\
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PERF_SAMPLE_BRANCH_HV)
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/* Contants to support power9 raw encoding format */
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#define p9_EVENT_COMBINE_SHIFT 10 /* Combine bit */
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#define p9_EVENT_COMBINE_MASK 0x3ull
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#define p9_EVENT_COMBINE(v) (((v) >> p9_EVENT_COMBINE_SHIFT) & p9_EVENT_COMBINE_MASK)
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#define p9_SDAR_MODE_SHIFT 50
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#define p9_SDAR_MODE_MASK 0x3ull
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#define p9_SDAR_MODE(v) (((v) >> p9_SDAR_MODE_SHIFT) & p9_SDAR_MODE_MASK)
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#define p9_EVENT_VALID_MASK \
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((p9_SDAR_MODE_MASK << p9_SDAR_MODE_SHIFT | \
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(EVENT_THRESH_MASK << EVENT_THRESH_SHIFT) | \
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(EVENT_SAMPLE_MASK << EVENT_SAMPLE_SHIFT) | \
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(EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT) | \
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(EVENT_PMC_MASK << EVENT_PMC_SHIFT) | \
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(EVENT_UNIT_MASK << EVENT_UNIT_SHIFT) | \
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(p9_EVENT_COMBINE_MASK << p9_EVENT_COMBINE_SHIFT) | \
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(EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \
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EVENT_LINUX_MASK | \
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EVENT_PSEL_MASK))
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/* Contants to support power10 raw encoding format */
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#define p10_SDAR_MODE_SHIFT 22
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#define p10_SDAR_MODE_MASK 0x3ull
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#define p10_SDAR_MODE(v) (((v) >> p10_SDAR_MODE_SHIFT) & \
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p10_SDAR_MODE_MASK)
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#define p10_EVENT_L2L3_SEL_MASK 0x1f
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#define p10_L2L3_SEL_SHIFT 3
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#define p10_L2L3_EVENT_SHIFT 40
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#define p10_EVENT_THRESH_MASK 0xffffull
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#define p10_EVENT_CACHE_SEL_MASK 0x3ull
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#define p10_EVENT_MMCR3_MASK 0x7fffull
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#define p10_EVENT_MMCR3_SHIFT 45
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#define p10_EVENT_VALID_MASK \
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((p10_SDAR_MODE_MASK << p10_SDAR_MODE_SHIFT | \
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(p10_EVENT_THRESH_MASK << EVENT_THRESH_SHIFT) | \
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(EVENT_SAMPLE_MASK << EVENT_SAMPLE_SHIFT) | \
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(p10_EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT) | \
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(EVENT_PMC_MASK << EVENT_PMC_SHIFT) | \
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(EVENT_UNIT_MASK << EVENT_UNIT_SHIFT) | \
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(p9_EVENT_COMBINE_MASK << p9_EVENT_COMBINE_SHIFT) | \
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(p10_EVENT_MMCR3_MASK << p10_EVENT_MMCR3_SHIFT) | \
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(EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \
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EVENT_LINUX_MASK | \
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EVENT_PSEL_MASK))
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/*
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* Layout of constraint bits:
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*
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* 60 56 52 48 44 40 36 32
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ]
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* |
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* thresh_sel -*
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*
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* 28 24 20 16 12 8 4 0
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* [ ] | [ ] [ sample ] [ ] [6] [5] [4] [3] [2] [1]
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* | | | |
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* BHRB IFM -* | | | Count of events for each PMC.
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* EBB -* | | p1, p2, p3, p4, p5, p6.
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* L1 I/D qualifier -* |
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* nc - number of counters -*
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*
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* The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
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* we want the low bit of each field to be added to any existing value.
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*
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* Everything else is a value field.
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*/
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#define CNST_FAB_MATCH_VAL(v) (((v) & EVENT_THR_CTL_MASK) << 56)
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#define CNST_FAB_MATCH_MASK CNST_FAB_MATCH_VAL(EVENT_THR_CTL_MASK)
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/* We just throw all the threshold bits into the constraint */
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#define CNST_THRESH_VAL(v) (((v) & EVENT_THRESH_MASK) << 32)
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#define CNST_THRESH_MASK CNST_THRESH_VAL(EVENT_THRESH_MASK)
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#define CNST_EBB_VAL(v) (((v) & EVENT_EBB_MASK) << 24)
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#define CNST_EBB_MASK CNST_EBB_VAL(EVENT_EBB_MASK)
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#define CNST_IFM_VAL(v) (((v) & EVENT_IFM_MASK) << 25)
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#define CNST_IFM_MASK CNST_IFM_VAL(EVENT_IFM_MASK)
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#define CNST_L1_QUAL_VAL(v) (((v) & 3) << 22)
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#define CNST_L1_QUAL_MASK CNST_L1_QUAL_VAL(3)
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#define CNST_SAMPLE_VAL(v) (((v) & EVENT_SAMPLE_MASK) << 16)
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#define CNST_SAMPLE_MASK CNST_SAMPLE_VAL(EVENT_SAMPLE_MASK)
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#define CNST_CACHE_GROUP_VAL(v) (((v) & 0xffull) << 55)
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#define CNST_CACHE_GROUP_MASK CNST_CACHE_GROUP_VAL(0xff)
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#define CNST_CACHE_PMC4_VAL (1ull << 54)
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#define CNST_CACHE_PMC4_MASK CNST_CACHE_PMC4_VAL
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#define CNST_L2L3_GROUP_VAL(v) (((v) & 0x1full) << 55)
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#define CNST_L2L3_GROUP_MASK CNST_L2L3_GROUP_VAL(0x1f)
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/*
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* For NC we are counting up to 4 events. This requires three bits, and we need
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* the fifth event to overflow and set the 4th bit. To achieve that we bias the
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* fields by 3 in test_adder.
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*/
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#define CNST_NC_SHIFT 12
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#define CNST_NC_VAL (1 << CNST_NC_SHIFT)
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#define CNST_NC_MASK (8 << CNST_NC_SHIFT)
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#define ISA207_TEST_ADDER (3 << CNST_NC_SHIFT)
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/*
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* For the per-PMC fields we have two bits. The low bit is added, so if two
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* events ask for the same PMC the sum will overflow, setting the high bit,
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* indicating an error. So our mask sets the high bit.
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*/
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#define CNST_PMC_SHIFT(pmc) ((pmc - 1) * 2)
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#define CNST_PMC_VAL(pmc) (1 << CNST_PMC_SHIFT(pmc))
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#define CNST_PMC_MASK(pmc) (2 << CNST_PMC_SHIFT(pmc))
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/* Our add_fields is defined as: */
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#define ISA207_ADD_FIELDS \
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CNST_PMC_VAL(1) | CNST_PMC_VAL(2) | CNST_PMC_VAL(3) | \
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CNST_PMC_VAL(4) | CNST_PMC_VAL(5) | CNST_PMC_VAL(6) | CNST_NC_VAL
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/* Bits in MMCR1 for PowerISA v2.07 */
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#define MMCR1_UNIT_SHIFT(pmc) (60 - (4 * ((pmc) - 1)))
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#define MMCR1_COMBINE_SHIFT(pmc) (35 - ((pmc) - 1))
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#define MMCR1_PMCSEL_SHIFT(pmc) (24 - (((pmc) - 1)) * 8)
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#define MMCR1_FAB_SHIFT 36
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#define MMCR1_DC_IC_QUAL_MASK 0x3
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#define MMCR1_DC_IC_QUAL_SHIFT 46
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/* MMCR1 Combine bits macro for power9 */
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#define p9_MMCR1_COMBINE_SHIFT(pmc) (38 - ((pmc - 1) * 2))
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/* Bits in MMCRA for PowerISA v2.07 */
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#define MMCRA_SAMP_MODE_SHIFT 1
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#define MMCRA_SAMP_ELIG_SHIFT 4
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#define MMCRA_THR_CTL_SHIFT 8
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#define MMCRA_THR_SEL_SHIFT 16
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#define MMCRA_THR_CMP_SHIFT 32
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#define MMCRA_SDAR_MODE_SHIFT 42
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#define MMCRA_SDAR_MODE_TLB (1ull << MMCRA_SDAR_MODE_SHIFT)
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#define MMCRA_SDAR_MODE_NO_UPDATES ~(0x3ull << MMCRA_SDAR_MODE_SHIFT)
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#define MMCRA_SDAR_MODE_DCACHE (2ull << MMCRA_SDAR_MODE_SHIFT)
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#define MMCRA_IFM_SHIFT 30
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#define MMCRA_THR_CTR_MANT_SHIFT 19
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#define MMCRA_THR_CTR_MANT_MASK 0x7Ful
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#define MMCRA_THR_CTR_MANT(v) (((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\
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MMCRA_THR_CTR_MANT_MASK)
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#define MMCRA_THR_CTR_EXP_SHIFT 27
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#define MMCRA_THR_CTR_EXP_MASK 0x7ul
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#define MMCRA_THR_CTR_EXP(v) (((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\
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MMCRA_THR_CTR_EXP_MASK)
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/* MMCRA Threshold Compare bit constant for power9 */
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#define p9_MMCRA_THR_CMP_SHIFT 45
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/* Bits in MMCR2 for PowerISA v2.07 */
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#define MMCR2_FCS(pmc) (1ull << (63 - (((pmc) - 1) * 9)))
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#define MMCR2_FCP(pmc) (1ull << (62 - (((pmc) - 1) * 9)))
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#define MMCR2_FCH(pmc) (1ull << (57 - (((pmc) - 1) * 9)))
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#define MAX_ALT 2
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#define MAX_PMU_COUNTERS 6
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/* Bits in MMCR3 for PowerISA v3.10 */
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#define MMCR3_SHIFT(pmc) (49 - (15 * ((pmc) - 1)))
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#define ISA207_SIER_TYPE_SHIFT 15
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#define ISA207_SIER_TYPE_MASK (0x7ull << ISA207_SIER_TYPE_SHIFT)
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#define ISA207_SIER_LDST_SHIFT 1
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#define ISA207_SIER_LDST_MASK (0x7ull << ISA207_SIER_LDST_SHIFT)
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#define ISA207_SIER_DATA_SRC_SHIFT 53
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#define ISA207_SIER_DATA_SRC_MASK (0x7ull << ISA207_SIER_DATA_SRC_SHIFT)
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#define P(a, b) PERF_MEM_S(a, b)
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#define PH(a, b) (P(LVL, HIT) | P(a, b))
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#define PM(a, b) (P(LVL, MISS) | P(a, b))
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int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp);
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int isa207_compute_mmcr(u64 event[], int n_ev,
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unsigned int hwc[], struct mmcr_regs *mmcr,
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struct perf_event *pevents[]);
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void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr);
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int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags,
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const unsigned int ev_alt[][MAX_ALT]);
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void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,
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struct pt_regs *regs);
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void isa207_get_mem_weight(u64 *weight);
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#endif
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