mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 12:42:17 +07:00
a023748d53
Pull x86 mm tree changes from Ingo Molnar: "The biggest change is full PAT support from Jürgen Gross: The x86 architecture offers via the PAT (Page Attribute Table) a way to specify different caching modes in page table entries. The PAT MSR contains 8 entries each specifying one of 6 possible cache modes. A pte references one of those entries via 3 bits: _PAGE_PAT, _PAGE_PWT and _PAGE_PCD. The Linux kernel currently supports only 4 different cache modes. The PAT MSR is set up in a way that the setting of _PAGE_PAT in a pte doesn't matter: the top 4 entries in the PAT MSR are the same as the 4 lower entries. This results in the kernel not supporting e.g. write-through mode. Especially this cache mode would speed up drivers of video cards which now have to use uncached accesses. OTOH some old processors (Pentium) don't support PAT correctly and the Xen hypervisor has been using a different PAT MSR configuration for some time now and can't change that as this setting is part of the ABI. This patch set abstracts the cache mode from the pte and introduces tables to translate between cache mode and pte bits (the default cache mode "write back" is hard-wired to PAT entry 0). The tables are statically initialized with values being compatible to old processors and current usage. As soon as the PAT MSR is changed (or - in case of Xen - is read at boot time) the tables are changed accordingly. Requests of mappings with special cache modes are always possible now, in case they are not supported there will be a fallback to a compatible but slower mode. Summing it up, this patch set adds the following features: - capability to support WT and WP cache modes on processors with full PAT support - processors with no or uncorrect PAT support are still working as today, even if WT or WP cache mode are selected by drivers for some pages - reduction of Xen special handling regarding cache mode Another change is a boot speedup on ridiculously large RAM systems, plus other smaller fixes" * 'x86-mm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits) x86: mm: Move PAT only functions to mm/pat.c xen: Support Xen pv-domains using PAT x86: Enable PAT to use cache mode translation tables x86: Respect PAT bit when copying pte values between large and normal pages x86: Support PAT bit in pagetable dump for lower levels x86: Clean up pgtable_types.h x86: Use new cache mode type in memtype related functions x86: Use new cache mode type in mm/ioremap.c x86: Use new cache mode type in setting page attributes x86: Remove looking for setting of _PAGE_PAT_LARGE in pageattr.c x86: Use new cache mode type in track_pfn_remap() and track_pfn_insert() x86: Use new cache mode type in mm/iomap_32.c x86: Use new cache mode type in asm/pgtable.h x86: Use new cache mode type in arch/x86/mm/init_64.c x86: Use new cache mode type in arch/x86/pci x86: Use new cache mode type in drivers/video/fbdev/vermilion x86: Use new cache mode type in drivers/video/fbdev/gbefb.c x86: Use new cache mode type in include/asm/fb.h x86: Make page cache mode a real type x86: mm: Use 2GB memory block size on large-memory x86-64 systems ...
438 lines
12 KiB
C
438 lines
12 KiB
C
/*
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* Re-map IO memory to kernel address space so that we can access it.
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* This is needed for high PCI addresses that aren't mapped in the
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* 640k-1MB IO memory area on PC's
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*
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* (C) Copyright 1995 1996 Linus Torvalds
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*/
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#include <linux/bootmem.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/vmalloc.h>
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#include <linux/mmiotrace.h>
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#include <asm/cacheflush.h>
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#include <asm/e820.h>
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#include <asm/fixmap.h>
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#include <asm/pgtable.h>
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#include <asm/tlbflush.h>
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#include <asm/pgalloc.h>
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#include <asm/pat.h>
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#include "physaddr.h"
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/*
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* Fix up the linear direct mapping of the kernel to avoid cache attribute
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* conflicts.
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*/
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int ioremap_change_attr(unsigned long vaddr, unsigned long size,
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enum page_cache_mode pcm)
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{
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unsigned long nrpages = size >> PAGE_SHIFT;
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int err;
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switch (pcm) {
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case _PAGE_CACHE_MODE_UC:
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default:
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err = _set_memory_uc(vaddr, nrpages);
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break;
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case _PAGE_CACHE_MODE_WC:
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err = _set_memory_wc(vaddr, nrpages);
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break;
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case _PAGE_CACHE_MODE_WB:
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err = _set_memory_wb(vaddr, nrpages);
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break;
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}
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return err;
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}
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static int __ioremap_check_ram(unsigned long start_pfn, unsigned long nr_pages,
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void *arg)
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{
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unsigned long i;
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for (i = 0; i < nr_pages; ++i)
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if (pfn_valid(start_pfn + i) &&
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!PageReserved(pfn_to_page(start_pfn + i)))
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return 1;
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WARN_ONCE(1, "ioremap on RAM pfn 0x%lx\n", start_pfn);
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return 0;
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}
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/*
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* Remap an arbitrary physical address space into the kernel virtual
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* address space. Needed when the kernel wants to access high addresses
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* directly.
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*
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* NOTE! We need to allow non-page-aligned mappings too: we will obviously
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* have to convert them into an offset in a page-aligned mapping, but the
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* caller shouldn't need to know that small detail.
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*/
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static void __iomem *__ioremap_caller(resource_size_t phys_addr,
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unsigned long size, enum page_cache_mode pcm, void *caller)
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{
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unsigned long offset, vaddr;
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resource_size_t pfn, last_pfn, last_addr;
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const resource_size_t unaligned_phys_addr = phys_addr;
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const unsigned long unaligned_size = size;
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struct vm_struct *area;
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enum page_cache_mode new_pcm;
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pgprot_t prot;
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int retval;
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void __iomem *ret_addr;
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int ram_region;
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/* Don't allow wraparound or zero size */
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last_addr = phys_addr + size - 1;
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if (!size || last_addr < phys_addr)
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return NULL;
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if (!phys_addr_valid(phys_addr)) {
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printk(KERN_WARNING "ioremap: invalid physical address %llx\n",
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(unsigned long long)phys_addr);
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WARN_ON_ONCE(1);
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return NULL;
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}
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/*
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* Don't remap the low PCI/ISA area, it's always mapped..
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*/
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if (is_ISA_range(phys_addr, last_addr))
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return (__force void __iomem *)phys_to_virt(phys_addr);
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/*
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* Don't allow anybody to remap normal RAM that we're using..
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*/
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/* First check if whole region can be identified as RAM or not */
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ram_region = region_is_ram(phys_addr, size);
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if (ram_region > 0) {
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WARN_ONCE(1, "ioremap on RAM at 0x%lx - 0x%lx\n",
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(unsigned long int)phys_addr,
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(unsigned long int)last_addr);
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return NULL;
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}
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/* If could not be identified(-1), check page by page */
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if (ram_region < 0) {
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pfn = phys_addr >> PAGE_SHIFT;
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last_pfn = last_addr >> PAGE_SHIFT;
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if (walk_system_ram_range(pfn, last_pfn - pfn + 1, NULL,
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__ioremap_check_ram) == 1)
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return NULL;
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}
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/*
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* Mappings have to be page-aligned
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*/
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offset = phys_addr & ~PAGE_MASK;
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phys_addr &= PHYSICAL_PAGE_MASK;
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size = PAGE_ALIGN(last_addr+1) - phys_addr;
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retval = reserve_memtype(phys_addr, (u64)phys_addr + size,
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pcm, &new_pcm);
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if (retval) {
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printk(KERN_ERR "ioremap reserve_memtype failed %d\n", retval);
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return NULL;
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}
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if (pcm != new_pcm) {
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if (!is_new_memtype_allowed(phys_addr, size, pcm, new_pcm)) {
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printk(KERN_ERR
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"ioremap error for 0x%llx-0x%llx, requested 0x%x, got 0x%x\n",
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(unsigned long long)phys_addr,
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(unsigned long long)(phys_addr + size),
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pcm, new_pcm);
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goto err_free_memtype;
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}
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pcm = new_pcm;
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}
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prot = PAGE_KERNEL_IO;
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switch (pcm) {
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case _PAGE_CACHE_MODE_UC:
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default:
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prot = __pgprot(pgprot_val(prot) |
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cachemode2protval(_PAGE_CACHE_MODE_UC));
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break;
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case _PAGE_CACHE_MODE_UC_MINUS:
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prot = __pgprot(pgprot_val(prot) |
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cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS));
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break;
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case _PAGE_CACHE_MODE_WC:
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prot = __pgprot(pgprot_val(prot) |
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cachemode2protval(_PAGE_CACHE_MODE_WC));
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break;
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case _PAGE_CACHE_MODE_WB:
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break;
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}
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/*
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* Ok, go for it..
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*/
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area = get_vm_area_caller(size, VM_IOREMAP, caller);
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if (!area)
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goto err_free_memtype;
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area->phys_addr = phys_addr;
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vaddr = (unsigned long) area->addr;
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if (kernel_map_sync_memtype(phys_addr, size, pcm))
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goto err_free_area;
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if (ioremap_page_range(vaddr, vaddr + size, phys_addr, prot))
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goto err_free_area;
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ret_addr = (void __iomem *) (vaddr + offset);
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mmiotrace_ioremap(unaligned_phys_addr, unaligned_size, ret_addr);
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/*
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* Check if the request spans more than any BAR in the iomem resource
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* tree.
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*/
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WARN_ONCE(iomem_map_sanity_check(unaligned_phys_addr, unaligned_size),
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KERN_INFO "Info: mapping multiple BARs. Your kernel is fine.");
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return ret_addr;
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err_free_area:
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free_vm_area(area);
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err_free_memtype:
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free_memtype(phys_addr, phys_addr + size);
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return NULL;
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}
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/**
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* ioremap_nocache - map bus memory into CPU space
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* @phys_addr: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap_nocache performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*
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* This version of ioremap ensures that the memory is marked uncachable
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* on the CPU as well as honouring existing caching rules from things like
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* the PCI bus. Note that there are other caches and buffers on many
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* busses. In particular driver authors should read up on PCI writes
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*
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* It's useful if some control registers are in such an area and
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* write combining or read caching is not desirable:
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*
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* Must be freed with iounmap.
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*/
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void __iomem *ioremap_nocache(resource_size_t phys_addr, unsigned long size)
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{
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/*
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* Ideally, this should be:
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* pat_enabled ? _PAGE_CACHE_MODE_UC : _PAGE_CACHE_MODE_UC_MINUS;
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*
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* Till we fix all X drivers to use ioremap_wc(), we will use
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* UC MINUS.
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*/
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enum page_cache_mode pcm = _PAGE_CACHE_MODE_UC_MINUS;
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return __ioremap_caller(phys_addr, size, pcm,
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__builtin_return_address(0));
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}
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EXPORT_SYMBOL(ioremap_nocache);
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/**
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* ioremap_wc - map memory into CPU space write combined
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* @phys_addr: bus address of the memory
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* @size: size of the resource to map
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*
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* This version of ioremap ensures that the memory is marked write combining.
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* Write combining allows faster writes to some hardware devices.
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*
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* Must be freed with iounmap.
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*/
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void __iomem *ioremap_wc(resource_size_t phys_addr, unsigned long size)
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{
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if (pat_enabled)
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return __ioremap_caller(phys_addr, size, _PAGE_CACHE_MODE_WC,
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__builtin_return_address(0));
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else
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return ioremap_nocache(phys_addr, size);
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}
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EXPORT_SYMBOL(ioremap_wc);
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void __iomem *ioremap_cache(resource_size_t phys_addr, unsigned long size)
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{
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return __ioremap_caller(phys_addr, size, _PAGE_CACHE_MODE_WB,
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__builtin_return_address(0));
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}
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EXPORT_SYMBOL(ioremap_cache);
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void __iomem *ioremap_prot(resource_size_t phys_addr, unsigned long size,
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unsigned long prot_val)
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{
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return __ioremap_caller(phys_addr, size,
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pgprot2cachemode(__pgprot(prot_val)),
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__builtin_return_address(0));
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}
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EXPORT_SYMBOL(ioremap_prot);
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/**
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* iounmap - Free a IO remapping
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* @addr: virtual address from ioremap_*
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*
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* Caller must ensure there is only one unmapping for the same pointer.
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*/
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void iounmap(volatile void __iomem *addr)
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{
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struct vm_struct *p, *o;
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if ((void __force *)addr <= high_memory)
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return;
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/*
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* __ioremap special-cases the PCI/ISA range by not instantiating a
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* vm_area and by simply returning an address into the kernel mapping
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* of ISA space. So handle that here.
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*/
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if ((void __force *)addr >= phys_to_virt(ISA_START_ADDRESS) &&
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(void __force *)addr < phys_to_virt(ISA_END_ADDRESS))
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return;
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addr = (volatile void __iomem *)
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(PAGE_MASK & (unsigned long __force)addr);
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mmiotrace_iounmap(addr);
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/* Use the vm area unlocked, assuming the caller
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ensures there isn't another iounmap for the same address
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in parallel. Reuse of the virtual address is prevented by
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leaving it in the global lists until we're done with it.
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cpa takes care of the direct mappings. */
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p = find_vm_area((void __force *)addr);
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if (!p) {
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printk(KERN_ERR "iounmap: bad address %p\n", addr);
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dump_stack();
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return;
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}
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free_memtype(p->phys_addr, p->phys_addr + get_vm_area_size(p));
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/* Finally remove it */
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o = remove_vm_area((void __force *)addr);
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BUG_ON(p != o || o == NULL);
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kfree(p);
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}
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EXPORT_SYMBOL(iounmap);
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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void *xlate_dev_mem_ptr(phys_addr_t phys)
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{
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void *addr;
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unsigned long start = phys & PAGE_MASK;
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/* If page is RAM, we can use __va. Otherwise ioremap and unmap. */
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if (page_is_ram(start >> PAGE_SHIFT))
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return __va(phys);
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addr = (void __force *)ioremap_cache(start, PAGE_SIZE);
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if (addr)
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addr = (void *)((unsigned long)addr | (phys & ~PAGE_MASK));
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return addr;
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}
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void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr)
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{
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if (page_is_ram(phys >> PAGE_SHIFT))
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return;
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iounmap((void __iomem *)((unsigned long)addr & PAGE_MASK));
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return;
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}
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static pte_t bm_pte[PAGE_SIZE/sizeof(pte_t)] __page_aligned_bss;
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static inline pmd_t * __init early_ioremap_pmd(unsigned long addr)
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{
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/* Don't assume we're using swapper_pg_dir at this point */
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pgd_t *base = __va(read_cr3());
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pgd_t *pgd = &base[pgd_index(addr)];
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pud_t *pud = pud_offset(pgd, addr);
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pmd_t *pmd = pmd_offset(pud, addr);
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return pmd;
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}
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static inline pte_t * __init early_ioremap_pte(unsigned long addr)
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{
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return &bm_pte[pte_index(addr)];
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}
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bool __init is_early_ioremap_ptep(pte_t *ptep)
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{
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return ptep >= &bm_pte[0] && ptep < &bm_pte[PAGE_SIZE/sizeof(pte_t)];
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}
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void __init early_ioremap_init(void)
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{
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pmd_t *pmd;
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#ifdef CONFIG_X86_64
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BUILD_BUG_ON((fix_to_virt(0) + PAGE_SIZE) & ((1 << PMD_SHIFT) - 1));
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#else
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WARN_ON((fix_to_virt(0) + PAGE_SIZE) & ((1 << PMD_SHIFT) - 1));
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#endif
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early_ioremap_setup();
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pmd = early_ioremap_pmd(fix_to_virt(FIX_BTMAP_BEGIN));
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memset(bm_pte, 0, sizeof(bm_pte));
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pmd_populate_kernel(&init_mm, pmd, bm_pte);
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/*
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* The boot-ioremap range spans multiple pmds, for which
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* we are not prepared:
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*/
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#define __FIXADDR_TOP (-PAGE_SIZE)
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BUILD_BUG_ON((__fix_to_virt(FIX_BTMAP_BEGIN) >> PMD_SHIFT)
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!= (__fix_to_virt(FIX_BTMAP_END) >> PMD_SHIFT));
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#undef __FIXADDR_TOP
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if (pmd != early_ioremap_pmd(fix_to_virt(FIX_BTMAP_END))) {
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WARN_ON(1);
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printk(KERN_WARNING "pmd %p != %p\n",
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pmd, early_ioremap_pmd(fix_to_virt(FIX_BTMAP_END)));
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printk(KERN_WARNING "fix_to_virt(FIX_BTMAP_BEGIN): %08lx\n",
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fix_to_virt(FIX_BTMAP_BEGIN));
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printk(KERN_WARNING "fix_to_virt(FIX_BTMAP_END): %08lx\n",
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fix_to_virt(FIX_BTMAP_END));
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printk(KERN_WARNING "FIX_BTMAP_END: %d\n", FIX_BTMAP_END);
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printk(KERN_WARNING "FIX_BTMAP_BEGIN: %d\n",
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FIX_BTMAP_BEGIN);
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}
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}
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void __init __early_set_fixmap(enum fixed_addresses idx,
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phys_addr_t phys, pgprot_t flags)
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{
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unsigned long addr = __fix_to_virt(idx);
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pte_t *pte;
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if (idx >= __end_of_fixed_addresses) {
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BUG();
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return;
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}
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pte = early_ioremap_pte(addr);
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if (pgprot_val(flags))
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set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, flags));
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else
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pte_clear(&init_mm, addr, pte);
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__flush_tlb_one(addr);
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}
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