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1e1cfc7213
After reading the specs for the Faraday Technology FTDMAC020 found in the Gemini platform, it becomes pretty evident that this is just another PL08x derivative, and should be handled like such by simply extending the existing PL08x driver to handle the quirks in this hardware. This patch makes memcpy work and has been tested on the Gemini and also regression-tested on the Nomadik NHK15 using dmatest with 10 threads per channel without a hinch for hours. I have not implemented slave DMA in those codepaths, because this device (Gemini) does not use slave DMA, and it seems like devices using FTDMAC020 for device DMA have a slightly different register layout so some real hardware is needed to proceed with this. I left some FIXME etc in the code for this. I had to do some refactorings of some helper functions, but I have not split those into separate patches because these refactorings do not make much sense without the increased complexity of handling the FTDMAC020. The DMA test would hang the platform on me on the Gemini after a few thousand iterations, however after turning of the caches the problem immediately disappeared and I could run the DMA engine with 10 threads pers physical channel for days in a row without a crash. I think there is no problem with the DMA driver: instead it is something fishy in the FA526 cache handling code that get pretty heavily exercised by the DMA engine and we need to go and fix that instead. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
221 lines
7.5 KiB
C
221 lines
7.5 KiB
C
/* include/linux/amba/pl080.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* ARM PrimeCell PL080 DMA controller
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/* Note, there are some Samsung updates to this controller block which
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* make it not entierly compatible with the PL080 specification from
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* ARM. When in doubt, check the Samsung documentation first.
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*
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* The Samsung defines are PL080S, and add an extra control register,
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* the ability to move more than 2^11 counts of data and some extra
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* OneNAND features.
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*/
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#ifndef ASM_PL080_H
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#define ASM_PL080_H
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#define PL080_INT_STATUS (0x00)
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#define PL080_TC_STATUS (0x04)
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#define PL080_TC_CLEAR (0x08)
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#define PL080_ERR_STATUS (0x0C)
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#define PL080_ERR_CLEAR (0x10)
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#define PL080_RAW_TC_STATUS (0x14)
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#define PL080_RAW_ERR_STATUS (0x18)
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#define PL080_EN_CHAN (0x1c)
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#define PL080_SOFT_BREQ (0x20)
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#define PL080_SOFT_SREQ (0x24)
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#define PL080_SOFT_LBREQ (0x28)
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#define PL080_SOFT_LSREQ (0x2C)
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#define PL080_CONFIG (0x30)
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#define PL080_CONFIG_M2_BE BIT(2)
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#define PL080_CONFIG_M1_BE BIT(1)
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#define PL080_CONFIG_ENABLE BIT(0)
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#define PL080_SYNC (0x34)
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/* The Faraday Technology FTDMAC020 variant registers */
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#define FTDMAC020_CH_BUSY (0x20)
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/* Identical to PL080_CONFIG */
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#define FTDMAC020_CSR (0x24)
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/* Identical to PL080_SYNC */
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#define FTDMAC020_SYNC (0x2C)
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#define FTDMAC020_REVISION (0x30)
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#define FTDMAC020_FEATURE (0x34)
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/* Per channel configuration registers */
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#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
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#define PL080_CH_SRC_ADDR (0x00)
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#define PL080_CH_DST_ADDR (0x04)
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#define PL080_CH_LLI (0x08)
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#define PL080_CH_CONTROL (0x0C)
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#define PL080_CH_CONFIG (0x10)
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#define PL080S_CH_CONTROL2 (0x10)
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#define PL080S_CH_CONFIG (0x14)
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/* The Faraday FTDMAC020 derivative shuffles the registers around */
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#define FTDMAC020_CH_CSR (0x00)
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#define FTDMAC020_CH_CFG (0x04)
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#define FTDMAC020_CH_SRC_ADDR (0x08)
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#define FTDMAC020_CH_DST_ADDR (0x0C)
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#define FTDMAC020_CH_LLP (0x10)
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#define FTDMAC020_CH_SIZE (0x14)
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#define PL080_LLI_ADDR_MASK (0x3fffffff << 2)
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#define PL080_LLI_ADDR_SHIFT (2)
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#define PL080_LLI_LM_AHB2 BIT(0)
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#define PL080_CONTROL_TC_IRQ_EN BIT(31)
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#define PL080_CONTROL_PROT_MASK (0x7 << 28)
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#define PL080_CONTROL_PROT_SHIFT (28)
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#define PL080_CONTROL_PROT_CACHE BIT(30)
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#define PL080_CONTROL_PROT_BUFF BIT(29)
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#define PL080_CONTROL_PROT_SYS BIT(28)
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#define PL080_CONTROL_DST_INCR BIT(27)
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#define PL080_CONTROL_SRC_INCR BIT(26)
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#define PL080_CONTROL_DST_AHB2 BIT(25)
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#define PL080_CONTROL_SRC_AHB2 BIT(24)
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#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21)
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#define PL080_CONTROL_DWIDTH_SHIFT (21)
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#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18)
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#define PL080_CONTROL_SWIDTH_SHIFT (18)
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#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15)
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#define PL080_CONTROL_DB_SIZE_SHIFT (15)
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#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12)
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#define PL080_CONTROL_SB_SIZE_SHIFT (12)
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#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0)
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#define PL080S_CONTROL_TRANSFER_SIZE_MASK (0x1ffffff << 0)
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#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
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#define PL080_BSIZE_1 (0x0)
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#define PL080_BSIZE_4 (0x1)
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#define PL080_BSIZE_8 (0x2)
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#define PL080_BSIZE_16 (0x3)
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#define PL080_BSIZE_32 (0x4)
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#define PL080_BSIZE_64 (0x5)
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#define PL080_BSIZE_128 (0x6)
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#define PL080_BSIZE_256 (0x7)
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#define PL080_WIDTH_8BIT (0x0)
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#define PL080_WIDTH_16BIT (0x1)
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#define PL080_WIDTH_32BIT (0x2)
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#define PL080N_CONFIG_ITPROT BIT(20)
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#define PL080N_CONFIG_SECPROT BIT(19)
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#define PL080_CONFIG_HALT BIT(18)
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#define PL080_CONFIG_ACTIVE BIT(17) /* RO */
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#define PL080_CONFIG_LOCK BIT(16)
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#define PL080_CONFIG_TC_IRQ_MASK BIT(15)
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#define PL080_CONFIG_ERR_IRQ_MASK BIT(14)
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#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11)
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#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
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#define PL080_CONFIG_DST_SEL_MASK (0xf << 6)
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#define PL080_CONFIG_DST_SEL_SHIFT (6)
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#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1)
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#define PL080_CONFIG_SRC_SEL_SHIFT (1)
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#define PL080_CONFIG_ENABLE BIT(0)
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#define PL080_FLOW_MEM2MEM (0x0)
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#define PL080_FLOW_MEM2PER (0x1)
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#define PL080_FLOW_PER2MEM (0x2)
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#define PL080_FLOW_SRC2DST (0x3)
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#define PL080_FLOW_SRC2DST_DST (0x4)
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#define PL080_FLOW_MEM2PER_PER (0x5)
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#define PL080_FLOW_PER2MEM_PER (0x6)
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#define PL080_FLOW_SRC2DST_SRC (0x7)
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#define FTDMAC020_CH_CSR_TC_MSK BIT(31)
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/* Later versions have a threshold in bits 24..26, */
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#define FTDMAC020_CH_CSR_FIFOTH_MSK (0x7 << 24)
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#define FTDMAC020_CH_CSR_FIFOTH_SHIFT (24)
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#define FTDMAC020_CH_CSR_CHPR1_MSK (0x3 << 22)
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#define FTDMAC020_CH_CSR_PROT3 BIT(21)
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#define FTDMAC020_CH_CSR_PROT2 BIT(20)
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#define FTDMAC020_CH_CSR_PROT1 BIT(19)
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#define FTDMAC020_CH_CSR_SRC_SIZE_MSK (0x7 << 16)
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#define FTDMAC020_CH_CSR_SRC_SIZE_SHIFT (16)
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#define FTDMAC020_CH_CSR_ABT BIT(15)
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#define FTDMAC020_CH_CSR_SRC_WIDTH_MSK (0x7 << 11)
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#define FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT (11)
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#define FTDMAC020_CH_CSR_DST_WIDTH_MSK (0x7 << 8)
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#define FTDMAC020_CH_CSR_DST_WIDTH_SHIFT (8)
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#define FTDMAC020_CH_CSR_MODE BIT(7)
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/* 00 = increase, 01 = decrease, 10 = fix */
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#define FTDMAC020_CH_CSR_SRCAD_CTL_MSK (0x3 << 5)
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#define FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT (5)
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#define FTDMAC020_CH_CSR_DSTAD_CTL_MSK (0x3 << 3)
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#define FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT (3)
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#define FTDMAC020_CH_CSR_SRC_SEL BIT(2)
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#define FTDMAC020_CH_CSR_DST_SEL BIT(1)
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#define FTDMAC020_CH_CSR_EN BIT(0)
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/* FIFO threshold setting */
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#define FTDMAC020_CH_CSR_FIFOTH_1 (0x0)
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#define FTDMAC020_CH_CSR_FIFOTH_2 (0x1)
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#define FTDMAC020_CH_CSR_FIFOTH_4 (0x2)
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#define FTDMAC020_CH_CSR_FIFOTH_8 (0x3)
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#define FTDMAC020_CH_CSR_FIFOTH_16 (0x4)
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/* The FTDMAC020 supports 64bit wide transfers */
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#define FTDMAC020_WIDTH_64BIT (0x3)
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/* Address can be increased, decreased or fixed */
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#define FTDMAC020_CH_CSR_SRCAD_CTL_INC (0x0)
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#define FTDMAC020_CH_CSR_SRCAD_CTL_DEC (0x1)
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#define FTDMAC020_CH_CSR_SRCAD_CTL_FIXED (0x2)
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#define FTDMAC020_CH_CFG_LLP_CNT_MASK (0xf << 16)
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#define FTDMAC020_CH_CFG_LLP_CNT_SHIFT (16)
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#define FTDMAC020_CH_CFG_BUSY BIT(8)
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#define FTDMAC020_CH_CFG_INT_ABT_MASK BIT(2)
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#define FTDMAC020_CH_CFG_INT_ERR_MASK BIT(1)
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#define FTDMAC020_CH_CFG_INT_TC_MASK BIT(0)
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/* Inside the LLIs, the applicable CSR fields are mapped differently */
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#define FTDMAC020_LLI_TC_MSK BIT(28)
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#define FTDMAC020_LLI_SRC_WIDTH_MSK (0x7 << 25)
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#define FTDMAC020_LLI_SRC_WIDTH_SHIFT (25)
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#define FTDMAC020_LLI_DST_WIDTH_MSK (0x7 << 22)
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#define FTDMAC020_LLI_DST_WIDTH_SHIFT (22)
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#define FTDMAC020_LLI_SRCAD_CTL_MSK (0x3 << 20)
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#define FTDMAC020_LLI_SRCAD_CTL_SHIFT (20)
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#define FTDMAC020_LLI_DSTAD_CTL_MSK (0x3 << 18)
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#define FTDMAC020_LLI_DSTAD_CTL_SHIFT (18)
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#define FTDMAC020_LLI_SRC_SEL BIT(17)
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#define FTDMAC020_LLI_DST_SEL BIT(16)
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#define FTDMAC020_LLI_TRANSFER_SIZE_MASK (0xfff << 0)
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#define FTDMAC020_LLI_TRANSFER_SIZE_SHIFT (0)
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#define FTDMAC020_CFG_LLP_CNT_MASK (0x0f << 16)
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#define FTDMAC020_CFG_LLP_CNT_SHIFT (16)
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#define FTDMAC020_CFG_BUSY BIT(8)
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#define FTDMAC020_CFG_INT_ABT_MSK BIT(2)
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#define FTDMAC020_CFG_INT_ERR_MSK BIT(1)
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#define FTDMAC020_CFG_INT_TC_MSK BIT(0)
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/* DMA linked list chain structure */
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struct pl080_lli {
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u32 src_addr;
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u32 dst_addr;
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u32 next_lli;
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u32 control0;
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};
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struct pl080s_lli {
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u32 src_addr;
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u32 dst_addr;
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u32 next_lli;
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u32 control0;
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u32 control1;
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};
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#endif /* ASM_PL080_H */
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