Eric Anholt 032838f9cb drm/pl111: Register the clock divider and use it. ... This is required for the panel to work on bcm911360, where CLCDCLK is the fixed 200Mhz AXI41 clock. The rate set is still passed up to the CLCDCLK, for platforms that have a settable rate on that one. v2: Set SET_RATE_PARENT (caught by Linus Walleij), depend on COMMON_CLK. v3: Mark the clk_ops static (caught by Stephen). Signed-off-by: Eric Anholt <eric@anholt.net> Link: http://patchwork.freedesktop.org/patch/msgid/20170508193348.30236-1-eric@anholt.net Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>		2017-05-19 11:11:35 -07:00
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bus.h	tty: amba-pl011: probe ZTE device from AMBA bus with a pseudo-ID	2016-08-31 15:24:23 +02:00
clcd-regs.h	drm/pl111: Register the clock divider and use it.	2017-05-19 11:11:35 -07:00
clcd.h	video: ARM CLCD: Move registers to a separate header.	2017-05-08 12:24:06 -07:00
kmi.h
mmci.h
pl08x.h	dmaengine: pl08x: Add support for the DMA slave map	2016-11-17 15:51:28 +05:30
pl022.h
pl080.h	dmaengine: pl08x: Use the BIT() macro consistently	2017-05-04 16:05:41 +05:30
pl093.h
serial.h	tty: amba-pl011: define flag register bits for ZTE device	2016-08-31 15:24:23 +02:00
sp810.h