mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 20:06:43 +07:00
e6e2df69c8
Rework portal mapping for PPC and ARM. The PPC devices require a cacheable coherent mapping while ARM will work with a non-cachable/write combine mapping. This also eliminates the need for manual cache flushes on ARM. This also fixes the code so sparse checking is clean. Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
79 lines
3.1 KiB
C
79 lines
3.1 KiB
C
/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include "dpaa_sys.h"
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#include <soc/fsl/bman.h>
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/* Portal processing (interrupt) sources */
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#define BM_PIRQ_RCRI 0x00000002 /* RCR Ring (below threshold) */
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/* Revision info (for errata and feature handling) */
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#define BMAN_REV10 0x0100
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#define BMAN_REV20 0x0200
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#define BMAN_REV21 0x0201
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extern u16 bman_ip_rev; /* 0 if uninitialised, otherwise BMAN_REVx */
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extern struct gen_pool *bm_bpalloc;
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struct bm_portal_config {
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/* Portal addresses */
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void *addr_virt_ce;
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void __iomem *addr_virt_ci;
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/* Allow these to be joined in lists */
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struct list_head list;
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struct device *dev;
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/* User-visible portal configuration settings */
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/* portal is affined to this cpu */
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int cpu;
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/* portal interrupt line */
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int irq;
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};
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struct bman_portal *bman_create_affine_portal(
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const struct bm_portal_config *config);
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/*
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* The below bman_p_***() variant might be called in a situation that the cpu
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* which the portal affine to is not online yet.
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* @bman_portal specifies which portal the API will use.
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*/
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int bman_p_irqsource_add(struct bman_portal *p, u32 bits);
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/*
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* Used by all portal interrupt registers except 'inhibit'
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* This mask contains all the "irqsource" bits visible to API users
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*/
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#define BM_PIRQ_VISIBLE BM_PIRQ_RCRI
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const struct bm_portal_config *
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bman_get_bm_portal_config(const struct bman_portal *portal);
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