mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 19:36:44 +07:00
565d0998ec
New AMD processors (Family 0x10 models 8+) support the Pause Filter Feature. This feature creates a new field in the VMCB called Pause Filter Count. If Pause Filter Count is greater than 0 and intercepting PAUSEs is enabled, the processor will increment an internal counter when a PAUSE instruction occurs instead of intercepting. When the internal counter reaches the Pause Filter Count value, a PAUSE intercept will occur. This feature can be used to detect contended spinlocks, especially when the lock holding VCPU is not scheduled. Rescheduling another VCPU prevents the VCPU seeking the lock from wasting its quantum by spinning idly. Experimental results show that most spinlocks are held for less than 1000 PAUSE cycles or more than a few thousand. Default the Pause Filter Counter to 3000 to detect the contended spinlocks. Processor support for this feature is indicated by a CPUID bit. On a 24 core system running 4 guests each with 16 VCPUs, this patch improved overall performance of each guest's 32 job kernbench by approximately 3-5% when combined with a scheduler algorithm thati caused the VCPU to sleep for a brief period. Further performance improvement may be possible with a more sophisticated yield algorithm. Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
327 lines
8.0 KiB
C
327 lines
8.0 KiB
C
#ifndef __SVM_H
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#define __SVM_H
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enum {
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INTERCEPT_INTR,
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INTERCEPT_NMI,
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INTERCEPT_SMI,
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INTERCEPT_INIT,
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INTERCEPT_VINTR,
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INTERCEPT_SELECTIVE_CR0,
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INTERCEPT_STORE_IDTR,
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INTERCEPT_STORE_GDTR,
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INTERCEPT_STORE_LDTR,
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INTERCEPT_STORE_TR,
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INTERCEPT_LOAD_IDTR,
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INTERCEPT_LOAD_GDTR,
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INTERCEPT_LOAD_LDTR,
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INTERCEPT_LOAD_TR,
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INTERCEPT_RDTSC,
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INTERCEPT_RDPMC,
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INTERCEPT_PUSHF,
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INTERCEPT_POPF,
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INTERCEPT_CPUID,
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INTERCEPT_RSM,
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INTERCEPT_IRET,
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INTERCEPT_INTn,
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INTERCEPT_INVD,
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INTERCEPT_PAUSE,
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INTERCEPT_HLT,
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INTERCEPT_INVLPG,
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INTERCEPT_INVLPGA,
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INTERCEPT_IOIO_PROT,
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INTERCEPT_MSR_PROT,
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INTERCEPT_TASK_SWITCH,
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INTERCEPT_FERR_FREEZE,
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INTERCEPT_SHUTDOWN,
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INTERCEPT_VMRUN,
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INTERCEPT_VMMCALL,
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INTERCEPT_VMLOAD,
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INTERCEPT_VMSAVE,
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INTERCEPT_STGI,
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INTERCEPT_CLGI,
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INTERCEPT_SKINIT,
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INTERCEPT_RDTSCP,
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INTERCEPT_ICEBP,
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INTERCEPT_WBINVD,
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INTERCEPT_MONITOR,
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INTERCEPT_MWAIT,
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INTERCEPT_MWAIT_COND,
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};
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struct __attribute__ ((__packed__)) vmcb_control_area {
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u16 intercept_cr_read;
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u16 intercept_cr_write;
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u16 intercept_dr_read;
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u16 intercept_dr_write;
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u32 intercept_exceptions;
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u64 intercept;
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u8 reserved_1[42];
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u16 pause_filter_count;
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u64 iopm_base_pa;
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u64 msrpm_base_pa;
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u64 tsc_offset;
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u32 asid;
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u8 tlb_ctl;
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u8 reserved_2[3];
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u32 int_ctl;
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u32 int_vector;
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u32 int_state;
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u8 reserved_3[4];
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u32 exit_code;
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u32 exit_code_hi;
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u64 exit_info_1;
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u64 exit_info_2;
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u32 exit_int_info;
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u32 exit_int_info_err;
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u64 nested_ctl;
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u8 reserved_4[16];
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u32 event_inj;
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u32 event_inj_err;
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u64 nested_cr3;
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u64 lbr_ctl;
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u8 reserved_5[832];
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};
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#define TLB_CONTROL_DO_NOTHING 0
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#define TLB_CONTROL_FLUSH_ALL_ASID 1
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#define V_TPR_MASK 0x0f
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#define V_IRQ_SHIFT 8
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#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
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#define V_INTR_PRIO_SHIFT 16
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#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
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#define V_IGN_TPR_SHIFT 20
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#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
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#define V_INTR_MASKING_SHIFT 24
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#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
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#define SVM_INTERRUPT_SHADOW_MASK 1
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#define SVM_IOIO_STR_SHIFT 2
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#define SVM_IOIO_REP_SHIFT 3
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#define SVM_IOIO_SIZE_SHIFT 4
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#define SVM_IOIO_ASIZE_SHIFT 7
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#define SVM_IOIO_TYPE_MASK 1
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#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
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#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
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#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
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#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
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struct __attribute__ ((__packed__)) vmcb_seg {
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u16 selector;
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u16 attrib;
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u32 limit;
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u64 base;
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};
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struct __attribute__ ((__packed__)) vmcb_save_area {
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struct vmcb_seg es;
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struct vmcb_seg cs;
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struct vmcb_seg ss;
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struct vmcb_seg ds;
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struct vmcb_seg fs;
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struct vmcb_seg gs;
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struct vmcb_seg gdtr;
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struct vmcb_seg ldtr;
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struct vmcb_seg idtr;
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struct vmcb_seg tr;
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u8 reserved_1[43];
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u8 cpl;
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u8 reserved_2[4];
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u64 efer;
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u8 reserved_3[112];
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u64 cr4;
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u64 cr3;
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u64 cr0;
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u64 dr7;
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u64 dr6;
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u64 rflags;
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u64 rip;
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u8 reserved_4[88];
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u64 rsp;
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u8 reserved_5[24];
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u64 rax;
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u64 star;
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u64 lstar;
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u64 cstar;
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u64 sfmask;
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u64 kernel_gs_base;
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u64 sysenter_cs;
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u64 sysenter_esp;
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u64 sysenter_eip;
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u64 cr2;
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u8 reserved_6[32];
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u64 g_pat;
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u64 dbgctl;
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u64 br_from;
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u64 br_to;
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u64 last_excp_from;
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u64 last_excp_to;
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};
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struct __attribute__ ((__packed__)) vmcb {
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struct vmcb_control_area control;
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struct vmcb_save_area save;
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};
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#define SVM_CPUID_FEATURE_SHIFT 2
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#define SVM_CPUID_FUNC 0x8000000a
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#define SVM_VM_CR_SVM_DISABLE 4
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#define SVM_SELECTOR_S_SHIFT 4
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#define SVM_SELECTOR_DPL_SHIFT 5
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#define SVM_SELECTOR_P_SHIFT 7
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#define SVM_SELECTOR_AVL_SHIFT 8
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#define SVM_SELECTOR_L_SHIFT 9
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#define SVM_SELECTOR_DB_SHIFT 10
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#define SVM_SELECTOR_G_SHIFT 11
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#define SVM_SELECTOR_TYPE_MASK (0xf)
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#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
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#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
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#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
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#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
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#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
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#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
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#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
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#define SVM_SELECTOR_WRITE_MASK (1 << 1)
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#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
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#define SVM_SELECTOR_CODE_MASK (1 << 3)
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#define INTERCEPT_CR0_MASK 1
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#define INTERCEPT_CR3_MASK (1 << 3)
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#define INTERCEPT_CR4_MASK (1 << 4)
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#define INTERCEPT_CR8_MASK (1 << 8)
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#define INTERCEPT_DR0_MASK 1
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#define INTERCEPT_DR1_MASK (1 << 1)
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#define INTERCEPT_DR2_MASK (1 << 2)
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#define INTERCEPT_DR3_MASK (1 << 3)
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#define INTERCEPT_DR4_MASK (1 << 4)
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#define INTERCEPT_DR5_MASK (1 << 5)
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#define INTERCEPT_DR6_MASK (1 << 6)
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#define INTERCEPT_DR7_MASK (1 << 7)
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#define SVM_EVTINJ_VEC_MASK 0xff
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#define SVM_EVTINJ_TYPE_SHIFT 8
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#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
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#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
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#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
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#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
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#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
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#define SVM_EVTINJ_VALID (1 << 31)
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#define SVM_EVTINJ_VALID_ERR (1 << 11)
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#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
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#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
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#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
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#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
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#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
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#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
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#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
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#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
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#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
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#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
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#define SVM_EXIT_READ_CR0 0x000
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#define SVM_EXIT_READ_CR3 0x003
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#define SVM_EXIT_READ_CR4 0x004
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#define SVM_EXIT_READ_CR8 0x008
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#define SVM_EXIT_WRITE_CR0 0x010
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#define SVM_EXIT_WRITE_CR3 0x013
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#define SVM_EXIT_WRITE_CR4 0x014
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#define SVM_EXIT_WRITE_CR8 0x018
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#define SVM_EXIT_READ_DR0 0x020
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#define SVM_EXIT_READ_DR1 0x021
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#define SVM_EXIT_READ_DR2 0x022
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#define SVM_EXIT_READ_DR3 0x023
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#define SVM_EXIT_READ_DR4 0x024
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#define SVM_EXIT_READ_DR5 0x025
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#define SVM_EXIT_READ_DR6 0x026
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#define SVM_EXIT_READ_DR7 0x027
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#define SVM_EXIT_WRITE_DR0 0x030
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#define SVM_EXIT_WRITE_DR1 0x031
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#define SVM_EXIT_WRITE_DR2 0x032
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#define SVM_EXIT_WRITE_DR3 0x033
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#define SVM_EXIT_WRITE_DR4 0x034
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#define SVM_EXIT_WRITE_DR5 0x035
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#define SVM_EXIT_WRITE_DR6 0x036
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#define SVM_EXIT_WRITE_DR7 0x037
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#define SVM_EXIT_EXCP_BASE 0x040
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#define SVM_EXIT_INTR 0x060
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#define SVM_EXIT_NMI 0x061
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#define SVM_EXIT_SMI 0x062
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#define SVM_EXIT_INIT 0x063
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#define SVM_EXIT_VINTR 0x064
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#define SVM_EXIT_CR0_SEL_WRITE 0x065
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#define SVM_EXIT_IDTR_READ 0x066
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#define SVM_EXIT_GDTR_READ 0x067
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#define SVM_EXIT_LDTR_READ 0x068
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#define SVM_EXIT_TR_READ 0x069
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#define SVM_EXIT_IDTR_WRITE 0x06a
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#define SVM_EXIT_GDTR_WRITE 0x06b
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#define SVM_EXIT_LDTR_WRITE 0x06c
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#define SVM_EXIT_TR_WRITE 0x06d
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#define SVM_EXIT_RDTSC 0x06e
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#define SVM_EXIT_RDPMC 0x06f
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#define SVM_EXIT_PUSHF 0x070
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#define SVM_EXIT_POPF 0x071
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#define SVM_EXIT_CPUID 0x072
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#define SVM_EXIT_RSM 0x073
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#define SVM_EXIT_IRET 0x074
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#define SVM_EXIT_SWINT 0x075
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#define SVM_EXIT_INVD 0x076
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#define SVM_EXIT_PAUSE 0x077
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#define SVM_EXIT_HLT 0x078
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#define SVM_EXIT_INVLPG 0x079
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#define SVM_EXIT_INVLPGA 0x07a
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#define SVM_EXIT_IOIO 0x07b
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#define SVM_EXIT_MSR 0x07c
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#define SVM_EXIT_TASK_SWITCH 0x07d
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#define SVM_EXIT_FERR_FREEZE 0x07e
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#define SVM_EXIT_SHUTDOWN 0x07f
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#define SVM_EXIT_VMRUN 0x080
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#define SVM_EXIT_VMMCALL 0x081
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#define SVM_EXIT_VMLOAD 0x082
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#define SVM_EXIT_VMSAVE 0x083
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#define SVM_EXIT_STGI 0x084
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#define SVM_EXIT_CLGI 0x085
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#define SVM_EXIT_SKINIT 0x086
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#define SVM_EXIT_RDTSCP 0x087
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#define SVM_EXIT_ICEBP 0x088
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#define SVM_EXIT_WBINVD 0x089
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#define SVM_EXIT_MONITOR 0x08a
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#define SVM_EXIT_MWAIT 0x08b
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#define SVM_EXIT_MWAIT_COND 0x08c
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#define SVM_EXIT_NPF 0x400
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#define SVM_EXIT_ERR -1
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#define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */
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#define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
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#define SVM_VMRUN ".byte 0x0f, 0x01, 0xd8"
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#define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
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#define SVM_CLGI ".byte 0x0f, 0x01, 0xdd"
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#define SVM_STGI ".byte 0x0f, 0x01, 0xdc"
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#define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"
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#endif
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