linux_dsm_epyc7002/arch/x86/events
Kan Liang 52e92f409d perf/x86/cstate: Add Tiger Lake CPU support
Tiger Lake is the followon to Ice Lake. From the perspective of Intel
cstate residency counters, there is nothing changed compared with
Ice Lake.

Share icl_cstates with Ice Lake.
Update the comments for Tiger Lake.

The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.

The patch has been tested on real hardware.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-10-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-10-12 15:13:09 +02:00
..
amd perf/x86/amd: Change/fix NMI latency mitigation to use a timestamp 2019-10-09 12:44:14 +02:00
intel perf/x86/cstate: Add Tiger Lake CPU support 2019-10-12 15:13:09 +02:00
core.c Merge branch 'x86-mm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 2019-09-16 19:21:34 -07:00
Kconfig
Makefile perf/x86: Add MSR probe interface 2019-06-24 19:28:31 +02:00
msr.c perf/x86/msr: Add Tiger Lake CPU support 2019-10-12 15:13:09 +02:00
perf_event.h perf/x86/intel: Support PEBS output to PT 2019-08-28 11:29:39 +02:00
probe.c perf/x86: Add MSR probe interface 2019-06-24 19:28:31 +02:00
probe.h perf/x86: Add MSR probe interface 2019-06-24 19:28:31 +02:00