mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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dbb799c397
RoCE and iSCSI would require some added/changed hw configuration in order to properly run; The biggest single change being the requirement of allocating and mapping host memory for several HW blocks that aren't being used by qede [SRC, QM, TM, etc.]. In addition, whereas qede is only using context memory for HW blocks, the new protocol would also require task memories to be added. Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
177 lines
3.3 KiB
C
177 lines
3.3 KiB
C
/* QLogic qed NIC Driver
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* Copyright (c) 2015 QLogic Corporation
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*
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* This software is available under the terms of the GNU General Public License
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* (GPL) Version 2, available from the file COPYING in the main directory of
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* this source tree.
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*/
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#ifndef _QED_CXT_H
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#define _QED_CXT_H
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/qed/qed_if.h>
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#include "qed_hsi.h"
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#include "qed.h"
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struct qed_cxt_info {
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void *p_cxt;
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u32 iid;
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enum protocol_type type;
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};
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#define MAX_TID_BLOCKS 512
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struct qed_tid_mem {
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u32 tid_size;
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u32 num_tids_per_block;
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u32 waste;
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u8 *blocks[MAX_TID_BLOCKS]; /* 4K */
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};
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/**
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* @brief qed_cxt_acquire - Acquire a new cid of a specific protocol type
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*
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* @param p_hwfn
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* @param type
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* @param p_cid
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*
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* @return int
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*/
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int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
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enum protocol_type type,
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u32 *p_cid);
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/**
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* @brief qedo_cid_get_cxt_info - Returns the context info for a specific cid
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*
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*
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* @param p_hwfn
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* @param p_info in/out
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*
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* @return int
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*/
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int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn,
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struct qed_cxt_info *p_info);
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/**
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* @brief qed_cxt_get_tid_mem_info
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*
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* @param p_hwfn
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* @param p_info
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*
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* @return int
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*/
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int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn,
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struct qed_tid_mem *p_info);
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#define QED_CXT_ISCSI_TID_SEG PROTOCOLID_ISCSI
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#define QED_CXT_ROCE_TID_SEG PROTOCOLID_ROCE
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enum qed_cxt_elem_type {
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QED_ELEM_CXT,
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QED_ELEM_SRQ,
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QED_ELEM_TASK
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};
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u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn,
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enum protocol_type type, u32 *vf_cid);
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/**
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* @brief qed_cxt_set_pf_params - Set the PF params for cxt init
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*
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* @param p_hwfn
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*
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* @return int
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*/
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int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn);
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/**
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* @brief qed_cxt_cfg_ilt_compute - compute ILT init parameters
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*
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* @param p_hwfn
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*
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* @return int
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*/
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int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn);
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/**
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* @brief qed_cxt_mngr_alloc - Allocate and init the context manager struct
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*
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* @param p_hwfn
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*
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* @return int
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*/
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int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn);
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/**
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* @brief qed_cxt_mngr_free
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*
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* @param p_hwfn
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*/
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void qed_cxt_mngr_free(struct qed_hwfn *p_hwfn);
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/**
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* @brief qed_cxt_tables_alloc - Allocate ILT shadow, Searcher T2, acquired map
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*
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* @param p_hwfn
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*
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* @return int
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*/
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int qed_cxt_tables_alloc(struct qed_hwfn *p_hwfn);
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/**
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* @brief qed_cxt_mngr_setup - Reset the acquired CIDs
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*
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* @param p_hwfn
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*/
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void qed_cxt_mngr_setup(struct qed_hwfn *p_hwfn);
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/**
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* @brief qed_cxt_hw_init_common - Initailze ILT and DQ, common phase, per path.
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*
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*
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*
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* @param p_hwfn
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*/
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void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn);
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/**
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* @brief qed_cxt_hw_init_pf - Initailze ILT and DQ, PF phase, per path.
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*
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*
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*
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* @param p_hwfn
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*/
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void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn);
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/**
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* @brief qed_qm_init_pf - Initailze the QM PF phase, per path
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*
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* @param p_hwfn
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*/
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void qed_qm_init_pf(struct qed_hwfn *p_hwfn);
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/**
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* @brief Reconfigures QM pf on the fly
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*
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* @param p_hwfn
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* @param p_ptt
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*
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* @return int
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*/
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int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
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/**
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* @brief qed_cxt_release - Release a cid
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*
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* @param p_hwfn
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* @param cid
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*/
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void qed_cxt_release_cid(struct qed_hwfn *p_hwfn,
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u32 cid);
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#define QED_CTX_WORKING_MEM 0
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#define QED_CTX_FL_MEM 1
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#endif
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