Damien Lespiau 1d2b9526a7 drm/i915/skl: Restore the DDI translation tables when enabling PW1 ... I was dumping the DDI translation tables to make sure my patch updating the HDMI entry was doing the right thing when I noticed that the table was showing reset values after DPMS. And indeed, the DDI translation registers are in power well 1 on SKL, and so we're losing their values when shutting down eDP. Calling intel_prepare_ddi() on PW1 enabling re-programs the table. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2015-03-17 22:30:08 +01:00
..
drm	drm/i915/skl: Restore the DDI translation tables when enabling PW1	2015-03-17 22:30:08 +01:00
host1x	gpu: host1x: Provide a proper struct bus_type	2015-01-27 10:09:14 +01:00
ipu-v3	gpu: ipu-v3: do not divide by zero if the pixel clock is too large	2015-02-23 17:18:59 +01:00
vga	Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip	2014-10-13 16:23:15 +02:00
Makefile	gpu: host1x: Provide a proper struct bus_type	2015-01-27 10:09:14 +01:00