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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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7cd2e6e38c
{set,get}_msglevel is required to use netif_{err,dbg} macros.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
131 lines
3.1 KiB
C
131 lines
3.1 KiB
C
/*
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*
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* Alchemy Au1x00 ethernet driver include file
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*
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* Author: Pete Popov <ppopov@mvista.com>
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*
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* Copyright 2001 MontaVista Software Inc.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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*
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*/
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#define MAC_IOSIZE 0x10000
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#define NUM_RX_DMA 4 /* Au1x00 has 4 rx hardware descriptors */
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#define NUM_TX_DMA 4 /* Au1x00 has 4 tx hardware descriptors */
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#define NUM_RX_BUFFS 4
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#define NUM_TX_BUFFS 4
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#define MAX_BUF_SIZE 2048
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#define ETH_TX_TIMEOUT (HZ/4)
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#define MAC_MIN_PKT_SIZE 64
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#define MULTICAST_FILTER_LIMIT 64
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/*
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* Data Buffer Descriptor. Data buffers must be aligned on 32 byte
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* boundary for both, receive and transmit.
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*/
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typedef struct db_dest {
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struct db_dest *pnext;
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volatile u32 *vaddr;
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dma_addr_t dma_addr;
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} db_dest_t;
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/*
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* The transmit and receive descriptors are memory
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* mapped registers.
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*/
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typedef struct tx_dma {
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u32 status;
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u32 buff_stat;
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u32 len;
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u32 pad;
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} tx_dma_t;
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typedef struct rx_dma {
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u32 status;
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u32 buff_stat;
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u32 pad[2];
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} rx_dma_t;
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/*
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* MAC control registers, memory mapped.
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*/
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typedef struct mac_reg {
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u32 control;
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u32 mac_addr_high;
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u32 mac_addr_low;
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u32 multi_hash_high;
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u32 multi_hash_low;
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u32 mii_control;
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u32 mii_data;
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u32 flow_control;
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u32 vlan1_tag;
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u32 vlan2_tag;
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} mac_reg_t;
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struct au1000_private {
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db_dest_t *pDBfree;
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db_dest_t db[NUM_RX_BUFFS+NUM_TX_BUFFS];
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volatile rx_dma_t *rx_dma_ring[NUM_RX_DMA];
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volatile tx_dma_t *tx_dma_ring[NUM_TX_DMA];
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db_dest_t *rx_db_inuse[NUM_RX_DMA];
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db_dest_t *tx_db_inuse[NUM_TX_DMA];
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u32 rx_head;
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u32 tx_head;
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u32 tx_tail;
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u32 tx_full;
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int mac_id;
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int mac_enabled; /* whether MAC is currently enabled and running (req. for mdio) */
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int old_link; /* used by au1000_adjust_link */
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int old_speed;
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int old_duplex;
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struct phy_device *phy_dev;
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struct mii_bus *mii_bus;
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/* PHY configuration */
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int phy_static_config;
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int phy_search_highest_addr;
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int phy1_search_mac0;
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int phy_addr;
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int phy_busid;
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int phy_irq;
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/* These variables are just for quick access to certain regs addresses. */
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volatile mac_reg_t *mac; /* mac registers */
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volatile u32 *enable; /* address of MAC Enable Register */
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u32 vaddr; /* virtual address of rx/tx buffers */
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dma_addr_t dma_addr; /* dma address of rx/tx buffers */
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spinlock_t lock; /* Serialise access to device */
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u32 msg_enable;
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};
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