mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 16:57:40 +07:00
6fe082b0fb
The DRC needs to run at 300MHz to be functional. This was done so far using assigned-clocks in the device tree, but that is easy to forget, and doesn't provide any other guarantee than the rate is going to be roughly the one requested at probe time. Therefore it's pretty fragile, so let's just use the exclusive clock API to enforce it. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20200107165957.672435-2-maxime@cerno.tech
128 lines
3.0 KiB
C
128 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2016 Free Electrons
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*/
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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struct sun6i_drc {
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struct clk *bus_clk;
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struct clk *mod_clk;
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struct reset_control *reset;
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};
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static int sun6i_drc_bind(struct device *dev, struct device *master,
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void *data)
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{
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struct sun6i_drc *drc;
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int ret;
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drc = devm_kzalloc(dev, sizeof(*drc), GFP_KERNEL);
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if (!drc)
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return -ENOMEM;
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dev_set_drvdata(dev, drc);
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drc->reset = devm_reset_control_get(dev, NULL);
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if (IS_ERR(drc->reset)) {
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dev_err(dev, "Couldn't get our reset line\n");
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return PTR_ERR(drc->reset);
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}
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ret = reset_control_deassert(drc->reset);
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if (ret) {
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dev_err(dev, "Couldn't deassert our reset line\n");
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return ret;
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}
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drc->bus_clk = devm_clk_get(dev, "ahb");
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if (IS_ERR(drc->bus_clk)) {
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dev_err(dev, "Couldn't get our bus clock\n");
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ret = PTR_ERR(drc->bus_clk);
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goto err_assert_reset;
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}
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clk_prepare_enable(drc->bus_clk);
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drc->mod_clk = devm_clk_get(dev, "mod");
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if (IS_ERR(drc->mod_clk)) {
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dev_err(dev, "Couldn't get our mod clock\n");
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ret = PTR_ERR(drc->mod_clk);
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goto err_disable_bus_clk;
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}
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ret = clk_set_rate_exclusive(drc->mod_clk, 300000000);
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if (ret) {
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dev_err(dev, "Couldn't set the module clock frequency\n");
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goto err_disable_bus_clk;
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}
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clk_prepare_enable(drc->mod_clk);
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return 0;
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err_disable_bus_clk:
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clk_disable_unprepare(drc->bus_clk);
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err_assert_reset:
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reset_control_assert(drc->reset);
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return ret;
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}
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static void sun6i_drc_unbind(struct device *dev, struct device *master,
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void *data)
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{
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struct sun6i_drc *drc = dev_get_drvdata(dev);
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clk_rate_exclusive_put(drc->mod_clk);
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clk_disable_unprepare(drc->mod_clk);
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clk_disable_unprepare(drc->bus_clk);
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reset_control_assert(drc->reset);
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}
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static const struct component_ops sun6i_drc_ops = {
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.bind = sun6i_drc_bind,
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.unbind = sun6i_drc_unbind,
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};
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static int sun6i_drc_probe(struct platform_device *pdev)
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{
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return component_add(&pdev->dev, &sun6i_drc_ops);
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}
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static int sun6i_drc_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &sun6i_drc_ops);
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return 0;
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}
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static const struct of_device_id sun6i_drc_of_table[] = {
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{ .compatible = "allwinner,sun6i-a31-drc" },
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{ .compatible = "allwinner,sun6i-a31s-drc" },
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{ .compatible = "allwinner,sun8i-a23-drc" },
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{ .compatible = "allwinner,sun8i-a33-drc" },
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{ .compatible = "allwinner,sun9i-a80-drc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sun6i_drc_of_table);
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static struct platform_driver sun6i_drc_platform_driver = {
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.probe = sun6i_drc_probe,
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.remove = sun6i_drc_remove,
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.driver = {
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.name = "sun6i-drc",
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.of_match_table = sun6i_drc_of_table,
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},
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};
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module_platform_driver(sun6i_drc_platform_driver);
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MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
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MODULE_DESCRIPTION("Allwinner A31 Dynamic Range Control (DRC) Driver");
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MODULE_LICENSE("GPL");
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