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7d83d17795
Adding management registers that convey implementation specific characteristics. Those are useful for trace configuration and collection along with general trouble shooting. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
86 lines
3.5 KiB
Plaintext
86 lines
3.5 KiB
Plaintext
What: /sys/bus/coresight/devices/<memory_map>.tmc/trigger_cntr
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Disables write access to the Trace RAM by stopping the
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formatter after a defined number of words have been stored
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following the trigger event. Additional interface for this
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driver are expected to be added as it matures.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Defines the size, in 32-bit words, of the local RAM buffer.
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The value is read directly from HW register RSZ, 0x004.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the TMC status register. The value
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is read directly from HW register STS, 0x00C.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the TMC RAM Read Pointer register
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that is used to read entries from the Trace RAM over the APB
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interface. The value is read directly from HW register RRP,
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0x014.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the TMC RAM Write Pointer register
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that is used to sets the write pointer to write entries from
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the CoreSight bus into the Trace RAM. The value is read directly
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from HW register RWP, 0x018.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Similar to "trigger_cntr" above except that this value is
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read directly from HW register TRG, 0x01C.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the TMC Control register. The value
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is read directly from HW register CTL, 0x020.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffsr
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the TMC Formatter and Flush Status
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register. The value is read directly from HW register FFSR,
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0x300.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffcr
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the TMC Formatter and Flush Control
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register. The value is read directly from HW register FFCR,
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0x304.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/mode
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the TMC Mode register, which
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indicate the mode the device has been configured to enact. The
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The value is read directly from the MODE register, 0x028.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/devid
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the capabilities of the Coresight TMC.
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The value is read directly from the DEVID register, 0xFC8,
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