mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 19:24:27 +07:00
1cb3cbe732
Mali DP500 behaves differently from the rest of the Mali DP IP, in that it does not have a one-shot mode and keeps writing the content of the current frame to the provided memory area until stopped. As a way of emulating the one-shot behaviour, we are going to use the CVAL interrupt that is being raised at the start of each frame, during prefetch phase, to act as End-of-Write signal, but with a twist: we are going to disable the memory write engine right after we're notified that it has been enabled, using the knowledge that the bit controlling the enabling will only be acted upon on the next vblank/prefetch. CVAL interrupt will fire durint the next prefetch phase every time the global CVAL bit gets set, so we need a state byte to track the memory write enabling. We also need to pay attention during the disabling of the memory write engine as that requires the CVAL bit to be set in the control register, but we don't want to do that during an atomic commit, as it will write into the hardware a partial state. Reviewed-by: Brian Starkey <brian.starkey@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
73 lines
2.0 KiB
C
73 lines
2.0 KiB
C
/*
|
|
* (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
|
|
* Author: Liviu Dudau <Liviu.Dudau@arm.com>
|
|
*
|
|
* This program is free software and is provided to you under the terms of the
|
|
* GNU General Public License version 2 as published by the Free Software
|
|
* Foundation, and any use by you of this program is subject to the terms
|
|
* of such GNU licence.
|
|
*
|
|
* ARM Mali DP500/DP550/DP650 KMS/DRM driver structures
|
|
*/
|
|
|
|
#ifndef __MALIDP_DRV_H__
|
|
#define __MALIDP_DRV_H__
|
|
|
|
#include <linux/mutex.h>
|
|
#include <linux/wait.h>
|
|
#include <drm/drmP.h>
|
|
#include "malidp_hw.h"
|
|
|
|
#define MALIDP_CONFIG_VALID_INIT 0
|
|
#define MALIDP_CONFIG_VALID_DONE 1
|
|
#define MALIDP_CONFIG_START 0xd0
|
|
|
|
struct malidp_drm {
|
|
struct malidp_hw_device *dev;
|
|
struct drm_crtc crtc;
|
|
wait_queue_head_t wq;
|
|
struct drm_pending_vblank_event *event;
|
|
atomic_t config_valid;
|
|
u32 core_id;
|
|
};
|
|
|
|
#define crtc_to_malidp_device(x) container_of(x, struct malidp_drm, crtc)
|
|
|
|
struct malidp_plane {
|
|
struct drm_plane base;
|
|
struct malidp_hw_device *hwdev;
|
|
const struct malidp_layer *layer;
|
|
};
|
|
|
|
struct malidp_plane_state {
|
|
struct drm_plane_state base;
|
|
|
|
/* size of the required rotation memory if plane is rotated */
|
|
u32 rotmem_size;
|
|
/* internal format ID */
|
|
u8 format;
|
|
u8 n_planes;
|
|
};
|
|
|
|
#define to_malidp_plane(x) container_of(x, struct malidp_plane, base)
|
|
#define to_malidp_plane_state(x) container_of(x, struct malidp_plane_state, base)
|
|
|
|
struct malidp_crtc_state {
|
|
struct drm_crtc_state base;
|
|
u32 gamma_coeffs[MALIDP_COEFFTAB_NUM_COEFFS];
|
|
u32 coloradj_coeffs[MALIDP_COLORADJ_NUM_COEFFS];
|
|
struct malidp_se_config scaler_config;
|
|
/* Bitfield of all the planes that have requested a scaled output. */
|
|
u8 scaled_planes_mask;
|
|
};
|
|
|
|
#define to_malidp_crtc_state(x) container_of(x, struct malidp_crtc_state, base)
|
|
|
|
int malidp_de_planes_init(struct drm_device *drm);
|
|
int malidp_crtc_init(struct drm_device *drm);
|
|
|
|
/* often used combination of rotational bits */
|
|
#define MALIDP_ROTATED_MASK (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)
|
|
|
|
#endif /* __MALIDP_DRV_H__ */
|