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84eaaf7500
Add endpoint mode support for PCIe C5 controller in P2972-0000 platform with information about supplies, PHY, PERST GPIO and GPIO that controls PCIe reference clock coming from the host system. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> |
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Makefile | ||
tegra132-norrin.dts | ||
tegra132.dtsi | ||
tegra186-p2771-0000.dts | ||
tegra186-p3310.dtsi | ||
tegra186.dtsi | ||
tegra194-p2888.dtsi | ||
tegra194-p2972-0000.dts | ||
tegra194.dtsi | ||
tegra210-p2180.dtsi | ||
tegra210-p2371-0000.dts | ||
tegra210-p2371-2180.dts | ||
tegra210-p2530.dtsi | ||
tegra210-p2571.dts | ||
tegra210-p2595.dtsi | ||
tegra210-p2597.dtsi | ||
tegra210-p2894-0050-a08.dts | ||
tegra210-p2894.dtsi | ||
tegra210-p3450-0000.dts | ||
tegra210-smaug.dts | ||
tegra210.dtsi |