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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1c9d3df5e8
If PG_dcache_dirty is set for a page, we need to flush the source page before performing any copypage operation using a different virtual address. This fixes the copypage implementations for XScale, StrongARM and ARMv6. This patch fixes segmentation faults seen in the dynamic linker under the usage patterns in glibc 2.4/2.5. Signed-off-by: Richard Purdie <rpurdie@rpsys.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
140 lines
3.5 KiB
C
140 lines
3.5 KiB
C
/*
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* linux/arch/arm/mm/copypage-v6.c
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*
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* Copyright (C) 2002 Deep Blue Solutions Ltd, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/shmparam.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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#include "mm.h"
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#if SHMLBA > 16384
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#error FIX ME
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#endif
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#define from_address (0xffff8000)
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#define to_address (0xffffc000)
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static DEFINE_SPINLOCK(v6_lock);
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/*
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* Copy the user page. No aliasing to deal with so we can just
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* attack the kernel's existing mapping of these pages.
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*/
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static void v6_copy_user_page_nonaliasing(void *kto, const void *kfrom, unsigned long vaddr)
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{
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copy_page(kto, kfrom);
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}
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/*
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* Clear the user page. No aliasing to deal with so we can just
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* attack the kernel's existing mapping of this page.
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*/
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static void v6_clear_user_page_nonaliasing(void *kaddr, unsigned long vaddr)
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{
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clear_page(kaddr);
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}
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/*
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* Copy the page, taking account of the cache colour.
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*/
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static void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned long vaddr)
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{
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unsigned int offset = CACHE_COLOUR(vaddr);
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unsigned long from, to;
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struct page *page = virt_to_page(kfrom);
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if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
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__flush_dcache_page(page_mapping(page), page);
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/*
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* Discard data in the kernel mapping for the new page.
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* FIXME: needs this MCRR to be supported.
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*/
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__asm__("mcrr p15, 0, %1, %0, c6 @ 0xec401f06"
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:
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: "r" (kto),
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"r" ((unsigned long)kto + PAGE_SIZE - L1_CACHE_BYTES)
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: "cc");
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/*
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* Now copy the page using the same cache colour as the
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* pages ultimate destination.
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*/
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spin_lock(&v6_lock);
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set_pte_ext(TOP_PTE(from_address) + offset, pfn_pte(__pa(kfrom) >> PAGE_SHIFT, PAGE_KERNEL), 0);
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set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(__pa(kto) >> PAGE_SHIFT, PAGE_KERNEL), 0);
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from = from_address + (offset << PAGE_SHIFT);
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to = to_address + (offset << PAGE_SHIFT);
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flush_tlb_kernel_page(from);
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flush_tlb_kernel_page(to);
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copy_page((void *)to, (void *)from);
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spin_unlock(&v6_lock);
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}
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/*
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* Clear the user page. We need to deal with the aliasing issues,
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* so remap the kernel page into the same cache colour as the user
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* page.
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*/
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static void v6_clear_user_page_aliasing(void *kaddr, unsigned long vaddr)
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{
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unsigned int offset = CACHE_COLOUR(vaddr);
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unsigned long to = to_address + (offset << PAGE_SHIFT);
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/*
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* Discard data in the kernel mapping for the new page
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* FIXME: needs this MCRR to be supported.
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*/
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__asm__("mcrr p15, 0, %1, %0, c6 @ 0xec401f06"
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:
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: "r" (kaddr),
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"r" ((unsigned long)kaddr + PAGE_SIZE - L1_CACHE_BYTES)
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: "cc");
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/*
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* Now clear the page using the same cache colour as
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* the pages ultimate destination.
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*/
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spin_lock(&v6_lock);
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set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(__pa(kaddr) >> PAGE_SHIFT, PAGE_KERNEL), 0);
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flush_tlb_kernel_page(to);
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clear_page((void *)to);
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spin_unlock(&v6_lock);
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}
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struct cpu_user_fns v6_user_fns __initdata = {
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.cpu_clear_user_page = v6_clear_user_page_nonaliasing,
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.cpu_copy_user_page = v6_copy_user_page_nonaliasing,
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};
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static int __init v6_userpage_init(void)
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{
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if (cache_is_vipt_aliasing()) {
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cpu_user.cpu_clear_user_page = v6_clear_user_page_aliasing;
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cpu_user.cpu_copy_user_page = v6_copy_user_page_aliasing;
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}
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return 0;
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}
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core_initcall(v6_userpage_init);
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