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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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The Allwinner SoCs have a display engine composed of several controllers assembled differently depending on the SoC, the number and type of output they have, and the additional features they provide. A number of those are supported in Linux, with the matching bindings. Now that we have the DT validation in place, let's split into separate file and convert the device tree bindings for those controllers to schemas. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20200103152801.47254-1-maxime@cerno.tech
292 lines
6.1 KiB
YAML
292 lines
6.1 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-backend.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A10 Display Engine Backend Device Tree Bindings
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <mripard@kernel.org>
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description: |
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The display engine backend exposes layers and sprites to the system.
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properties:
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compatible:
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enum:
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- allwinner,sun4i-a10-display-backend
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- allwinner,sun5i-a13-display-backend
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- allwinner,sun6i-a31-display-backend
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- allwinner,sun7i-a20-display-backend
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- allwinner,sun8i-a23-display-backend
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- allwinner,sun8i-a33-display-backend
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- allwinner,sun9i-a80-display-backend
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reg:
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minItems: 1
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maxItems: 2
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items:
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- description: Display Backend registers
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- description: SAT registers
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reg-names:
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minItems: 1
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maxItems: 2
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items:
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- const: be
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- const: sat
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interrupts:
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maxItems: 1
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clocks:
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minItems: 3
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maxItems: 4
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items:
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- description: The backend interface clock
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- description: The backend module clock
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- description: The backend DRAM clock
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- description: The SAT clock
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clock-names:
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minItems: 3
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maxItems: 4
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items:
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- const: ahb
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- const: mod
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- const: ram
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- const: sat
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resets:
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minItems: 1
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maxItems: 2
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items:
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- description: The Backend reset line
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- description: The SAT reset line
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reset-names:
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minItems: 1
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maxItems: 2
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items:
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- const: be
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- const: sat
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# FIXME: This should be made required eventually once every SoC will
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# have the MBUS declared.
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interconnects:
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maxItems: 1
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# FIXME: This should be made required eventually once every SoC will
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# have the MBUS declared.
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interconnect-names:
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const: dma-mem
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ports:
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type: object
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description: |
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A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt.
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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port@0:
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type: object
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description: |
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Input endpoints of the controller.
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port@1:
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type: object
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description: |
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Output endpoints of the controller.
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required:
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- "#address-cells"
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- "#size-cells"
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- port@0
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- port@1
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- resets
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- ports
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additionalProperties: false
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if:
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properties:
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compatible:
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contains:
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const: allwinner,sun8i-a33-display-backend
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then:
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properties:
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reg:
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minItems: 2
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reg-names:
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minItems: 2
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clocks:
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minItems: 4
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clock-names:
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minItems: 4
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resets:
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minItems: 2
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reset-names:
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minItems: 2
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required:
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- reg-names
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- reset-names
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else:
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properties:
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reg:
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maxItems: 1
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reg-names:
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maxItems: 1
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clocks:
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maxItems: 3
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clock-names:
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maxItems: 3
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resets:
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maxItems: 1
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reset-names:
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maxItems: 1
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examples:
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- |
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/*
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* This comes from the clock/sun4i-a10-ccu.h and
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* reset/sun4i-a10-ccu.h headers, but we can't include them since
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* it would trigger a bunch of warnings for redefinitions of
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* symbols with the other example.
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*/
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#define CLK_AHB_DE_BE0 42
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#define CLK_DRAM_DE_BE0 140
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#define CLK_DE_BE0 144
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#define RST_DE_BE0 5
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display-backend@1e60000 {
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compatible = "allwinner,sun4i-a10-display-backend";
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reg = <0x01e60000 0x10000>;
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interrupts = <47>;
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clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
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<&ccu CLK_DRAM_DE_BE0>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&ccu RST_DE_BE0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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endpoint@0 {
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reg = <0>;
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remote-endpoint = <&fe0_out_be0>;
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};
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endpoint@1 {
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reg = <1>;
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remote-endpoint = <&fe1_out_be0>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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endpoint@0 {
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reg = <0>;
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remote-endpoint = <&tcon0_in_be0>;
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};
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endpoint@1 {
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reg = <1>;
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remote-endpoint = <&tcon1_in_be0>;
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};
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};
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};
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/*
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* This comes from the clock/sun8i-a23-a33-ccu.h and
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* reset/sun8i-a23-a33-ccu.h headers, but we can't include them
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* since it would trigger a bunch of warnings for redefinitions of
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* symbols with the other example.
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*/
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#define CLK_BUS_DE_BE 40
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#define CLK_BUS_SAT 46
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#define CLK_DRAM_DE_BE 84
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#define CLK_DE_BE 85
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#define RST_BUS_DE_BE 21
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#define RST_BUS_SAT 27
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display-backend@1e60000 {
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compatible = "allwinner,sun8i-a33-display-backend";
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reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
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reg-names = "be", "sat";
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
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clock-names = "ahb", "mod",
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"ram", "sat";
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resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
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reset-names = "be", "sat";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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endpoint {
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remote-endpoint = <&fe0_out_be0>;
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};
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};
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port@1 {
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reg = <1>;
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endpoint {
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remote-endpoint = <&drc0_in_be0>;
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};
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};
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};
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};
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...
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