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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f37a7767f6
This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC: - PSCI - CPU (single) - Cache controller - Main clocks and controller - Interrupt controller - Timer - PMU - Reset controller - Product register - System controller - UART for console Inspried by a patch by Takeshi Kihara in the BSP. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
128 lines
3.0 KiB
Plaintext
128 lines
3.0 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Device Tree Source for the r8a77990 SoC
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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*/
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "renesas,r8a77990";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* 1 core only at this point */
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a53_0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0>;
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device_type = "cpu";
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power-domains = <&sysc 5>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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};
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L2_CA53: cache-controller@0 {
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compatible = "cache";
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reg = <0>;
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power-domains = <&sysc 21>;
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cache-unified;
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cache-level = <2>;
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};
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};
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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pmu_a53 {
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compatible = "arm,cortex-a53-pmu";
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interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&a53_0>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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soc: soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a77990-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a77990-rst";
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reg = <0 0xe6160000 0 0x0200>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a77990-sysc";
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reg = <0 0xe6180000 0 0x0400>;
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#power-domain-cells = <1>;
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};
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scif2: serial@e6e88000 {
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compatible = "renesas,scif-r8a77990",
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"renesas,rcar-gen3-scif", "renesas,scif";
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reg = <0 0xe6e88000 0 64>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 310>;
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clock-names = "fck";
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power-domains = <&sysc 32>;
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resets = <&cpg 310>;
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status = "disabled";
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};
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gic: interrupt-controller@f1010000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xf1010000 0 0x1000>,
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<0x0 0xf1020000 0 0x20000>,
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<0x0 0xf1040000 0 0x20000>,
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<0x0 0xf1060000 0 0x20000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg CPG_MOD 408>;
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clock-names = "clk";
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power-domains = <&sysc 32>;
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resets = <&cpg 408>;
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};
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prr: chipid@fff00044 {
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compatible = "renesas,prr";
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reg = <0 0xfff00044 0 4>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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