mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 19:43:07 +07:00
4b9ffb5a35
This patch has the goal to add support for DesignWare UFS Controller specific operations. Signed-off-by: Joao Pinto <jpinto@synopsys.com> Reviewed-by: Hannes Reinicke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
37 lines
876 B
C
37 lines
876 B
C
/*
|
|
* UFS Host driver for Synopsys Designware Core
|
|
*
|
|
* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
|
|
*
|
|
* Authors: Joao Pinto <jpinto@synopsys.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#ifndef _UFSHCI_DWC_H
|
|
#define _UFSHCI_DWC_H
|
|
|
|
/* DWC HC UFSHCI specific Registers */
|
|
enum dwc_specific_registers {
|
|
DWC_UFS_REG_HCLKDIV = 0xFC,
|
|
};
|
|
|
|
/* Clock Divider Values: Hex equivalent of frequency in MHz */
|
|
enum clk_div_values {
|
|
DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e,
|
|
DWC_UFS_REG_HCLKDIV_DIV_125 = 0x7d,
|
|
DWC_UFS_REG_HCLKDIV_DIV_200 = 0xc8,
|
|
};
|
|
|
|
/* Selector Index */
|
|
enum selector_index {
|
|
SELIND_LN0_TX = 0x00,
|
|
SELIND_LN1_TX = 0x01,
|
|
SELIND_LN0_RX = 0x04,
|
|
SELIND_LN1_RX = 0x05,
|
|
};
|
|
|
|
#endif /* End of Header */
|