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231ece36f5
ENETC ports can manage the MDIO bus via local register interface. However there's also a centralized way to manage the MDIO bus, via the MDIO PCIe endpoint device integrated by the same root complex that also integrates the ENETC ports (eth controllers). Depending on board design and use case, centralized access to MDIO may be better than using local ENETC port registers. For instance, on the LS1028A QDS board where MDIO muxing is required. Also, the LS1028A on-chip switch doesn't have a local MDIO register interface. The current patch registers the above PCIe endpoint as a separate MDIO bus and provides a driver for it by re-using the code used for local MDIO access. It also allows the ENETC port PHYs to be managed by this driver if the local "mdio" node is missing from the ENETC port node. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
13 lines
325 B
C
13 lines
325 B
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/* Copyright 2019 NXP */
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#include <linux/phy.h>
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#include "enetc_pf.h"
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struct enetc_mdio_priv {
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struct enetc_hw *hw;
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};
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int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value);
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int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum);
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