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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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aa8d3e74f5
The Hip06 soc has same cpu topology compared with Hip05, four clusters and each cluster has quard Cortex-A57, but with different IO part, like HNS, SAS and PCI, they are all upgraded. There are also not same in ITS, MBIGEN and SMMU, etc. This patch adds the initial dts for hip06 d03 board. Note, there is no serial, because the soc use LPC uart, the serial node is not needed. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
35 lines
588 B
Plaintext
35 lines
588 B
Plaintext
/**
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* dts file for Hisilicon D03 Development Board
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*
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* Copyright (C) 2016 Hisilicon Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*
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*/
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/dts-v1/;
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#include "hip06.dtsi"
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/ {
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model = "Hisilicon Hip06 D03 Development Board";
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compatible = "hisilicon,hip06-d03";
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memory@00000000 {
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device_type = "memory";
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reg = <0x0 0x00000000 0x0 0x40000000>;
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};
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chosen { };
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};
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&usb_ohci {
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status = "ok";
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};
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&usb_ehci {
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status = "ok";
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};
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