mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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600f7cfebe
Makes use of the proc_comm interface to provide clock control on MSM7X01A family SoCs. Signed-off-by: Brian Swetland <swetland@google.com>
127 lines
4.7 KiB
C
127 lines
4.7 KiB
C
/* arch/arm/mach-msm/clock-7x01a.c
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*
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* Clock tables for MSM7X01A
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*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2007 QUALCOMM Incorporated
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include "clock.h"
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#include "devices.h"
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/* clock IDs used by the modem processor */
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#define ACPU_CLK 0 /* Applications processor clock */
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#define ADM_CLK 1 /* Applications data mover clock */
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#define ADSP_CLK 2 /* ADSP clock */
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#define EBI1_CLK 3 /* External bus interface 1 clock */
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#define EBI2_CLK 4 /* External bus interface 2 clock */
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#define ECODEC_CLK 5 /* External CODEC clock */
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#define EMDH_CLK 6 /* External MDDI host clock */
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#define GP_CLK 7 /* General purpose clock */
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#define GRP_CLK 8 /* Graphics clock */
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#define I2C_CLK 9 /* I2C clock */
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#define ICODEC_RX_CLK 10 /* Internal CODEX RX clock */
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#define ICODEC_TX_CLK 11 /* Internal CODEX TX clock */
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#define IMEM_CLK 12 /* Internal graphics memory clock */
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#define MDC_CLK 13 /* MDDI client clock */
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#define MDP_CLK 14 /* Mobile display processor clock */
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#define PBUS_CLK 15 /* Peripheral bus clock */
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#define PCM_CLK 16 /* PCM clock */
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#define PMDH_CLK 17 /* Primary MDDI host clock */
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#define SDAC_CLK 18 /* Stereo DAC clock */
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#define SDC1_CLK 19 /* Secure Digital Card clocks */
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#define SDC1_PCLK 20
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#define SDC2_CLK 21
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#define SDC2_PCLK 22
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#define SDC3_CLK 23
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#define SDC3_PCLK 24
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#define SDC4_CLK 25
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#define SDC4_PCLK 26
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#define TSIF_CLK 27 /* Transport Stream Interface clocks */
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#define TSIF_REF_CLK 28
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#define TV_DAC_CLK 29 /* TV clocks */
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#define TV_ENC_CLK 30
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#define UART1_CLK 31 /* UART clocks */
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#define UART2_CLK 32
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#define UART3_CLK 33
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#define UART1DM_CLK 34
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#define UART2DM_CLK 35
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#define USB_HS_CLK 36 /* High speed USB core clock */
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#define USB_HS_PCLK 37 /* High speed USB pbus clock */
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#define USB_OTG_CLK 38 /* Full speed USB clock */
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#define VDC_CLK 39 /* Video controller clock */
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#define VFE_CLK 40 /* Camera / Video Front End clock */
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#define VFE_MDC_CLK 41 /* VFE MDDI client clock */
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#define NR_CLKS 42
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#define CLOCK(clk_name, clk_id, clk_dev, clk_flags) { \
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.name = clk_name, \
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.id = clk_id, \
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.flags = clk_flags, \
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.dev = clk_dev, \
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}
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#define OFF CLKFLAG_AUTO_OFF
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#define MINMAX CLKFLAG_USE_MIN_MAX_TO_SET
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struct clk msm_clocks[] = {
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CLOCK("adm_clk", ADM_CLK, NULL, 0),
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CLOCK("adsp_clk", ADSP_CLK, NULL, 0),
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CLOCK("ebi1_clk", EBI1_CLK, NULL, 0),
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CLOCK("ebi2_clk", EBI2_CLK, NULL, 0),
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CLOCK("ecodec_clk", ECODEC_CLK, NULL, 0),
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CLOCK("emdh_clk", EMDH_CLK, NULL, OFF),
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CLOCK("gp_clk", GP_CLK, NULL, 0),
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CLOCK("grp_clk", GRP_CLK, NULL, OFF),
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CLOCK("i2c_clk", I2C_CLK, &msm_device_i2c.dev, 0),
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CLOCK("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0),
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CLOCK("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0),
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CLOCK("imem_clk", IMEM_CLK, NULL, OFF),
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CLOCK("mdc_clk", MDC_CLK, NULL, 0),
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CLOCK("mdp_clk", MDP_CLK, NULL, OFF),
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CLOCK("pbus_clk", PBUS_CLK, NULL, 0),
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CLOCK("pcm_clk", PCM_CLK, NULL, 0),
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CLOCK("pmdh_clk", PMDH_CLK, NULL, OFF | MINMAX),
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CLOCK("sdac_clk", SDAC_CLK, NULL, OFF),
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CLOCK("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF),
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CLOCK("sdc_pclk", SDC1_PCLK, &msm_device_sdc1.dev, OFF),
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CLOCK("sdc_clk", SDC2_CLK, &msm_device_sdc2.dev, OFF),
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CLOCK("sdc_pclk", SDC2_PCLK, &msm_device_sdc2.dev, OFF),
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CLOCK("sdc_clk", SDC3_CLK, &msm_device_sdc3.dev, OFF),
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CLOCK("sdc_pclk", SDC3_PCLK, &msm_device_sdc3.dev, OFF),
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CLOCK("sdc_clk", SDC4_CLK, &msm_device_sdc4.dev, OFF),
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CLOCK("sdc_pclk", SDC4_PCLK, &msm_device_sdc4.dev, OFF),
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CLOCK("tsif_clk", TSIF_CLK, NULL, 0),
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CLOCK("tsif_ref_clk", TSIF_REF_CLK, NULL, 0),
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CLOCK("tv_dac_clk", TV_DAC_CLK, NULL, 0),
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CLOCK("tv_enc_clk", TV_ENC_CLK, NULL, 0),
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CLOCK("uart_clk", UART1_CLK, &msm_device_uart1.dev, OFF),
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CLOCK("uart_clk", UART2_CLK, &msm_device_uart2.dev, 0),
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CLOCK("uart_clk", UART3_CLK, &msm_device_uart3.dev, OFF),
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CLOCK("uart1dm_clk", UART1DM_CLK, NULL, OFF),
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CLOCK("uart2dm_clk", UART2DM_CLK, NULL, 0),
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CLOCK("usb_hs_clk", USB_HS_CLK, &msm_device_hsusb.dev, OFF),
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CLOCK("usb_hs_pclk", USB_HS_PCLK, &msm_device_hsusb.dev, OFF),
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CLOCK("usb_otg_clk", USB_OTG_CLK, NULL, 0),
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CLOCK("vdc_clk", VDC_CLK, NULL, OFF | MINMAX),
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CLOCK("vfe_clk", VFE_CLK, NULL, OFF),
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CLOCK("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF),
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};
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unsigned msm_num_clocks = ARRAY_SIZE(msm_clocks);
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