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2bfba3c444
Suggested-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
248 lines
7.5 KiB
C
248 lines
7.5 KiB
C
/*
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* Copyright (C) 1996-1998 Linus Torvalds & authors (see below)
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*/
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/*
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* Authors:
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* Jaromir Koutek <miri@punknet.cz>,
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* Jan Harkes <jaharkes@cwi.nl>,
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* Mark Lord <mlord@pobox.com>
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* Some parts of code are from ali14xx.c and from rz1000.c.
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*
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* OPTi is trademark of OPTi, Octek is trademark of Octek.
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*
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* I used docs from OPTi databook, from ftp.opti.com, file 9123-0002.ps
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* and disassembled/traced setupvic.exe (DOS program).
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* It increases kernel code about 2 kB.
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* I don't have this card no more, but I hope I can get some in case
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* of needed development.
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* My card is Octek PIDE 1.01 (on card) or OPTiViC (program).
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* It has a place for a secondary connector in circuit, but nothing
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* is there. Also BIOS says no address for
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* secondary controller (see bellow in ide_init_opti621).
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* I've only tested this on my system, which only has one disk.
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* It's Western Digital WDAC2850, with PIO mode 3. The PCI bus
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* is at 20 MHz (I have DX2/80, I tried PCI at 40, but I got random
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* lockups). I tried the OCTEK double speed CD-ROM and
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* it does not work! But I can't boot DOS also, so it's probably
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* hardware fault. I have connected Conner 80MB, the Seagate 850MB (no
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* problems) and Seagate 1GB (as slave, WD as master). My experiences
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* with the third, 1GB drive: I got 3MB/s (hdparm), but sometimes
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* it slows to about 100kB/s! I don't know why and I have
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* not this drive now, so I can't try it again.
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* I write this driver because I lost the paper ("manual") with
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* settings of jumpers on the card and I have to boot Linux with
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* Loadlin except LILO, cause I have to run the setupvic.exe program
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* already or I get disk errors (my test: rpm -Vf
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* /usr/X11R6/bin/XF86_SVGA - or any big file).
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* Some numbers from hdparm -t /dev/hda:
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* Timing buffer-cache reads: 32 MB in 3.02 seconds =10.60 MB/sec
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* Timing buffered disk reads: 16 MB in 5.52 seconds = 2.90 MB/sec
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* I have 4 Megs/s before, but I don't know why (maybe changes
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* in hdparm test).
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* After release of 0.1, I got some successful reports, so it might work.
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*
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* The main problem with OPTi is that some timings for master
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* and slave must be the same. For example, if you have master
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* PIO 3 and slave PIO 0, driver have to set some timings of
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* master for PIO 0. Second problem is that opti621_set_pio_mode
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* got only one drive to set, but have to set both drives.
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* This is solved in compute_pios. If you don't set
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* the second drive, compute_pios use ide_get_best_pio_mode
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* for autoselect mode (you can change it to PIO 0, if you want).
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* If you then set the second drive to another PIO, the old value
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* (automatically selected) will be overrided by yours.
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* There is a 25/33MHz switch in configuration
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* register, but driver is written for use at any frequency.
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*
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* Version 0.1, Nov 8, 1996
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* by Jaromir Koutek, for 2.1.8.
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* Initial version of driver.
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*
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* Version 0.2
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* Number 0.2 skipped.
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*
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* Version 0.3, Nov 29, 1997
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* by Mark Lord (probably), for 2.1.68
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* Updates for use with new IDE block driver.
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*
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* Version 0.4, Dec 14, 1997
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* by Jan Harkes
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* Fixed some errors and cleaned the code.
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*
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* Version 0.5, Jan 2, 1998
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* by Jaromir Koutek
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* Updates for use with (again) new IDE block driver.
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* Update of documentation.
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*
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* Version 0.6, Jan 2, 1999
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* by Jaromir Koutek
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* Reversed to version 0.3 of the driver, because
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* 0.5 doesn't work.
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#include <asm/io.h>
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#define DRV_NAME "opti621"
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#define READ_REG 0 /* index of Read cycle timing register */
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#define WRITE_REG 1 /* index of Write cycle timing register */
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#define CNTRL_REG 3 /* index of Control register */
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#define STRAP_REG 5 /* index of Strap register */
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#define MISC_REG 6 /* index of Miscellaneous register */
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static int reg_base;
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static DEFINE_SPINLOCK(opti621_lock);
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/* Write value to register reg, base of register
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* is at reg_base (0x1f0 primary, 0x170 secondary,
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* if not changed by PCI configuration).
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* This is from setupvic.exe program.
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*/
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static void write_reg(u8 value, int reg)
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{
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inw(reg_base + 1);
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inw(reg_base + 1);
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outb(3, reg_base + 2);
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outb(value, reg_base + reg);
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outb(0x83, reg_base + 2);
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}
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/* Read value from register reg, base of register
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* is at reg_base (0x1f0 primary, 0x170 secondary,
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* if not changed by PCI configuration).
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* This is from setupvic.exe program.
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*/
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static u8 read_reg(int reg)
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{
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u8 ret = 0;
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inw(reg_base + 1);
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inw(reg_base + 1);
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outb(3, reg_base + 2);
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ret = inb(reg_base + reg);
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outb(0x83, reg_base + 2);
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return ret;
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}
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static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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ide_hwif_t *hwif = drive->hwif;
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ide_drive_t *pair = ide_get_pair_dev(drive);
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unsigned long flags;
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u8 tim, misc, addr_pio = pio, clk;
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/* DRDY is default 2 (by OPTi Databook) */
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static const u8 addr_timings[2][5] = {
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{ 0x20, 0x10, 0x00, 0x00, 0x00 }, /* 33 MHz */
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{ 0x10, 0x10, 0x00, 0x00, 0x00 }, /* 25 MHz */
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};
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static const u8 data_rec_timings[2][5] = {
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{ 0x5b, 0x45, 0x32, 0x21, 0x20 }, /* 33 MHz */
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{ 0x48, 0x34, 0x21, 0x10, 0x10 } /* 25 MHz */
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};
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drive->drive_data = XFER_PIO_0 + pio;
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if (pair) {
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if (pair->drive_data && pair->drive_data < drive->drive_data)
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addr_pio = pair->drive_data - XFER_PIO_0;
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}
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spin_lock_irqsave(&opti621_lock, flags);
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reg_base = hwif->io_ports.data_addr;
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/* allow Register-B */
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outb(0xc0, reg_base + CNTRL_REG);
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/* hmm, setupvic.exe does this ;-) */
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outb(0xff, reg_base + 5);
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/* if reads 0xff, adapter not exist? */
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(void)inb(reg_base + CNTRL_REG);
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/* if reads 0xc0, no interface exist? */
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read_reg(CNTRL_REG);
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/* check CLK speed */
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clk = read_reg(STRAP_REG) & 1;
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printk(KERN_INFO "%s: CLK = %d MHz\n", hwif->name, clk ? 25 : 33);
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tim = data_rec_timings[clk][pio];
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misc = addr_timings[clk][addr_pio];
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/* select Index-0/1 for Register-A/B */
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write_reg(drive->dn & 1, MISC_REG);
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/* set read cycle timings */
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write_reg(tim, READ_REG);
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/* set write cycle timings */
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write_reg(tim, WRITE_REG);
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/* use Register-A for drive 0 */
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/* use Register-B for drive 1 */
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write_reg(0x85, CNTRL_REG);
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/* set address setup, DRDY timings, */
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/* and read prefetch for both drives */
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write_reg(misc, MISC_REG);
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spin_unlock_irqrestore(&opti621_lock, flags);
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}
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static const struct ide_port_ops opti621_port_ops = {
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.set_pio_mode = opti621_set_pio_mode,
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};
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static const struct ide_port_info opti621_chipset __devinitdata = {
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.name = DRV_NAME,
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.enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
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.port_ops = &opti621_port_ops,
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.host_flags = IDE_HFLAG_NO_DMA,
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.pio_mask = ATA_PIO4,
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};
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static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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return ide_pci_init_one(dev, &opti621_chipset, NULL);
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}
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static const struct pci_device_id opti621_pci_tbl[] = {
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{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
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{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 0 },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);
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static struct pci_driver opti621_pci_driver = {
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.name = "Opti621_IDE",
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.id_table = opti621_pci_tbl,
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.probe = opti621_init_one,
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.remove = ide_pci_remove,
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.suspend = ide_pci_suspend,
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.resume = ide_pci_resume,
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};
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static int __init opti621_ide_init(void)
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{
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return ide_pci_register_driver(&opti621_pci_driver);
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}
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static void __exit opti621_ide_exit(void)
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{
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pci_unregister_driver(&opti621_pci_driver);
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}
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module_init(opti621_ide_init);
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module_exit(opti621_ide_exit);
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MODULE_AUTHOR("Jaromir Koutek, Jan Harkes, Mark Lord");
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MODULE_DESCRIPTION("PCI driver module for Opti621 IDE");
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MODULE_LICENSE("GPL");
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