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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e94f8cb32d
Some of the factors-style clocks on the A80 have different widths for the mux values in the registers. Add a .muxmask field to clk_factors_config to make it configurable. Passing a bitmask instead of a width parameter will allow reuse in case we support table-based muxes in the future. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
44 lines
870 B
C
44 lines
870 B
C
#ifndef __MACH_SUNXI_CLK_FACTORS_H
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#define __MACH_SUNXI_CLK_FACTORS_H
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/spinlock.h>
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#define SUNXI_FACTORS_NOT_APPLICABLE (0)
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struct clk_factors_config {
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u8 nshift;
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u8 nwidth;
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u8 kshift;
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u8 kwidth;
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u8 mshift;
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u8 mwidth;
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u8 pshift;
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u8 pwidth;
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u8 n_start;
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};
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struct factors_data {
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int enable;
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int mux;
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int muxmask;
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struct clk_factors_config *table;
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void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
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const char *name;
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};
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struct clk_factors {
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struct clk_hw hw;
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void __iomem *reg;
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struct clk_factors_config *config;
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void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
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spinlock_t *lock;
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};
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struct clk * __init sunxi_factors_register(struct device_node *node,
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const struct factors_data *data,
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spinlock_t *lock);
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#endif
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