Matthew Gerlach 8614afd689 fpga: dfl: fix bug in port reset handshake ... When putting the port in reset, driver must wait for the soft reset acknowledgment bit instead of the soft reset bit. Fixes: 47c1b19c16 (fpga: dfl: afu: add port ops support) Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Acked-by: Wu Hao <hao.wu@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>		2020-07-13 22:11:17 -07:00
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altera-cvp.c
altera-fpga2sdram.c
altera-freeze-bridge.c
altera-hps2fpga.c
altera-pr-ip-core-plat.c
altera-pr-ip-core.c
altera-ps-spi.c
dfl-afu-dma-region.c
dfl-afu-error.c
dfl-afu-main.c	fpga: dfl: fix bug in port reset handshake	2020-07-13 22:11:17 -07:00
dfl-afu-region.c
dfl-afu.h
dfl-fme-br.c
dfl-fme-error.c
dfl-fme-main.c
dfl-fme-mgr.c
dfl-fme-perf.c
dfl-fme-pr.c
dfl-fme-pr.h
dfl-fme-region.c
dfl-fme.h
dfl-pci.c	fpga: dfl: pci: reduce the scope of variable 'ret'	2020-07-13 22:11:17 -07:00
dfl.c
dfl.h
fpga-bridge.c
fpga-mgr.c
fpga-region.c
ice40-spi.c
Kconfig	FPGA Manager fixes for 5.8-rc1	2020-06-26 17:26:31 +02:00
machxo2-spi.c
Makefile
of-fpga-region.c
socfpga-a10.c
socfpga.c
stratix10-soc.c
ts73xx-fpga.c
xilinx-pr-decoupler.c
xilinx-spi.c
zynq-fpga.c
zynqmp-fpga.c