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1afc82aee4
The principles of operation says: The storage-operand fetch references of one instruction occur after those of all preceding instructions and before those of subsequent instructions, as observed by other CPUs and by channel programs. [...] The CPU may fetch the operands of instructions before the instructions are executed. [...] The CPU may delay placing results in storage. [...] the results of one instruction are placed in storage after the results of all preceding instructions have been placed in storage and before any results of the succeeding instructions are stored, as observed by other CPUs and by the channel subsystem. which boils down to: - reads are in order - writes are in order - reads can happen earlier - writes can happen later By definition (see memory-barrier.txt) read barriers orders reads vs reads and write barriers orders writes agains writes. but neither of these orders reads vs. writes. That means we can implement smp_wmb,smp_rmb,wmb and rmb as simple compiler barriers. To avoid reviewing all driver code for correct barrier usage we keep dma_[rw]mb as serialization for now. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
57 lines
1.3 KiB
C
57 lines
1.3 KiB
C
/*
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* Copyright IBM Corp. 1999, 2009
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*
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
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*/
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*/
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#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
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/* Fast-BCR without checkpoint synchronization */
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#define __ASM_BARRIER "bcr 14,0\n"
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#else
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#define __ASM_BARRIER "bcr 15,0\n"
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#endif
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#define mb() do { asm volatile(__ASM_BARRIER : : : "memory"); } while (0)
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#define rmb() barrier()
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#define wmb() barrier()
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#define dma_rmb() mb()
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#define dma_wmb() mb()
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define read_barrier_depends() do { } while (0)
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#define smp_read_barrier_depends() do { } while (0)
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#define smp_mb__before_atomic() smp_mb()
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#define smp_mb__after_atomic() smp_mb()
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#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0)
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#define smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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___p1; \
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})
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#endif /* __ASM_BARRIER_H */
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