mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 04:06:41 +07:00
b8845074cf
This patch creates an l4_core interconnect for OMAP3, and moves some of the generic peripherals under it. System control module nodes are moved under this new interconnect also, and the SCM clock layout is changed to use the renamed SCM node as the clock provider. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reported-by: Tony Lindgren <tony@atomide.com>
129 lines
3.0 KiB
Plaintext
129 lines
3.0 KiB
Plaintext
/*
|
|
* Device Tree Source for OMAP3 clock data
|
|
*
|
|
* Copyright (C) 2013 Texas Instruments, Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
&scm_clocks {
|
|
emac_ick: emac_ick {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,am35xx-gate-clock";
|
|
clocks = <&ipss_ick>;
|
|
reg = <0x059c>;
|
|
ti,bit-shift = <1>;
|
|
};
|
|
|
|
emac_fck: emac_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&rmii_ck>;
|
|
reg = <0x059c>;
|
|
ti,bit-shift = <9>;
|
|
};
|
|
|
|
vpfe_ick: vpfe_ick {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,am35xx-gate-clock";
|
|
clocks = <&ipss_ick>;
|
|
reg = <0x059c>;
|
|
ti,bit-shift = <2>;
|
|
};
|
|
|
|
vpfe_fck: vpfe_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&pclk_ck>;
|
|
reg = <0x059c>;
|
|
ti,bit-shift = <10>;
|
|
};
|
|
|
|
hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,am35xx-gate-clock";
|
|
clocks = <&ipss_ick>;
|
|
reg = <0x059c>;
|
|
ti,bit-shift = <0>;
|
|
};
|
|
|
|
hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&sys_ck>;
|
|
reg = <0x059c>;
|
|
ti,bit-shift = <8>;
|
|
};
|
|
|
|
hecc_ck: hecc_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,am35xx-gate-clock";
|
|
clocks = <&sys_ck>;
|
|
reg = <0x059c>;
|
|
ti,bit-shift = <3>;
|
|
};
|
|
};
|
|
&cm_clocks {
|
|
ipss_ick: ipss_ick {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,am35xx-interface-clock";
|
|
clocks = <&core_l3_ick>;
|
|
reg = <0x0a10>;
|
|
ti,bit-shift = <4>;
|
|
};
|
|
|
|
rmii_ck: rmii_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <50000000>;
|
|
};
|
|
|
|
pclk_ck: pclk_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <27000000>;
|
|
};
|
|
|
|
uart4_ick_am35xx: uart4_ick_am35xx {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&core_l4_ick>;
|
|
reg = <0x0a10>;
|
|
ti,bit-shift = <23>;
|
|
};
|
|
|
|
uart4_fck_am35xx: uart4_fck_am35xx {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&core_48m_fck>;
|
|
reg = <0x0a00>;
|
|
ti,bit-shift = <23>;
|
|
};
|
|
};
|
|
|
|
&cm_clockdomains {
|
|
core_l3_clkdm: core_l3_clkdm {
|
|
compatible = "ti,clockdomain";
|
|
clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
|
|
<&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
|
|
<&hecc_ck>;
|
|
};
|
|
|
|
core_l4_clkdm: core_l4_clkdm {
|
|
compatible = "ti,clockdomain";
|
|
clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
|
|
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
|
|
<&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
|
|
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
|
|
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
|
|
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
|
|
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
|
|
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
|
|
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
|
|
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
|
|
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
|
|
<&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
|
|
};
|
|
};
|