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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1618fdd960
Make sure that we have access to the performance counters and that they aren't being used by perf events or anything else. Cc: Will Deacon <will.deacon@arm.com> Cc: Jean Pihet <jpihet@mvista.com> Signed-off-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
416 lines
8.1 KiB
C
416 lines
8.1 KiB
C
/**
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* op_model_v7.c
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* ARM V7 (Cortex A8) Event Monitor Driver
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*
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* Copyright 2008 Jean Pihet <jpihet@mvista.com>
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* Copyright 2004 ARM SMP Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/oprofile.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/smp.h>
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#include <asm/pmu.h>
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#include "op_counter.h"
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#include "op_arm_model.h"
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#include "op_model_v7.h"
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/* #define DEBUG */
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/*
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* ARM V7 PMNC support
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*/
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static u32 cnt_en[CNTMAX];
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static inline void armv7_pmnc_write(u32 val)
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{
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val &= PMNC_MASK;
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asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (val));
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}
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static inline u32 armv7_pmnc_read(void)
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{
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u32 val;
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asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
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return val;
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}
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static inline u32 armv7_pmnc_enable_counter(unsigned int cnt)
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{
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u32 val;
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if (cnt >= CNTMAX) {
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printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter"
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" %d\n", smp_processor_id(), cnt);
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return -1;
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}
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if (cnt == CCNT)
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val = CNTENS_C;
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else
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val = (1 << (cnt - CNT0));
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val &= CNTENS_MASK;
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asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
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return cnt;
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}
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static inline u32 armv7_pmnc_disable_counter(unsigned int cnt)
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{
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u32 val;
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if (cnt >= CNTMAX) {
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printk(KERN_ERR "oprofile: CPU%u disabling wrong PMNC counter"
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" %d\n", smp_processor_id(), cnt);
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return -1;
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}
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if (cnt == CCNT)
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val = CNTENC_C;
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else
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val = (1 << (cnt - CNT0));
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val &= CNTENC_MASK;
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asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
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return cnt;
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}
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static inline u32 armv7_pmnc_enable_intens(unsigned int cnt)
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{
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u32 val;
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if (cnt >= CNTMAX) {
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printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter"
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" interrupt enable %d\n", smp_processor_id(), cnt);
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return -1;
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}
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if (cnt == CCNT)
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val = INTENS_C;
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else
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val = (1 << (cnt - CNT0));
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val &= INTENS_MASK;
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asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
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return cnt;
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}
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static inline u32 armv7_pmnc_getreset_flags(void)
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{
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u32 val;
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/* Read */
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asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
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/* Write to clear flags */
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val &= FLAG_MASK;
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asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
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return val;
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}
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static inline int armv7_pmnc_select_counter(unsigned int cnt)
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{
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u32 val;
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if ((cnt == CCNT) || (cnt >= CNTMAX)) {
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printk(KERN_ERR "oprofile: CPU%u selecting wrong PMNC counteri"
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" %d\n", smp_processor_id(), cnt);
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return -1;
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}
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val = (cnt - CNT0) & SELECT_MASK;
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asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
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return cnt;
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}
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static inline void armv7_pmnc_write_evtsel(unsigned int cnt, u32 val)
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{
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if (armv7_pmnc_select_counter(cnt) == cnt) {
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val &= EVTSEL_MASK;
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asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
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}
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}
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static void armv7_pmnc_reset_counter(unsigned int cnt)
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{
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u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt);
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u32 val = -(u32)counter_config[cpu_cnt].count;
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switch (cnt) {
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case CCNT:
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armv7_pmnc_disable_counter(cnt);
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asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (val));
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if (cnt_en[cnt] != 0)
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armv7_pmnc_enable_counter(cnt);
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break;
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case CNT0:
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case CNT1:
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case CNT2:
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case CNT3:
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armv7_pmnc_disable_counter(cnt);
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if (armv7_pmnc_select_counter(cnt) == cnt)
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asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (val));
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if (cnt_en[cnt] != 0)
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armv7_pmnc_enable_counter(cnt);
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break;
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default:
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printk(KERN_ERR "oprofile: CPU%u resetting wrong PMNC counter"
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" %d\n", smp_processor_id(), cnt);
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break;
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}
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}
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int armv7_setup_pmnc(void)
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{
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unsigned int cnt;
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if (armv7_pmnc_read() & PMNC_E) {
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printk(KERN_ERR "oprofile: CPU%u PMNC still enabled when setup"
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" new event counter.\n", smp_processor_id());
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return -EBUSY;
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}
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/* Initialize & Reset PMNC: C bit and P bit */
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armv7_pmnc_write(PMNC_P | PMNC_C);
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for (cnt = CCNT; cnt < CNTMAX; cnt++) {
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unsigned long event;
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u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt);
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/*
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* Disable counter
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*/
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armv7_pmnc_disable_counter(cnt);
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cnt_en[cnt] = 0;
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if (!counter_config[cpu_cnt].enabled)
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continue;
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event = counter_config[cpu_cnt].event & 255;
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/*
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* Set event (if destined for PMNx counters)
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* We don't need to set the event if it's a cycle count
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*/
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if (cnt != CCNT)
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armv7_pmnc_write_evtsel(cnt, event);
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/*
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* Enable interrupt for this counter
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*/
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armv7_pmnc_enable_intens(cnt);
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/*
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* Reset counter
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*/
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armv7_pmnc_reset_counter(cnt);
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/*
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* Enable counter
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*/
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armv7_pmnc_enable_counter(cnt);
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cnt_en[cnt] = 1;
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}
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return 0;
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}
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static inline void armv7_start_pmnc(void)
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{
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armv7_pmnc_write(armv7_pmnc_read() | PMNC_E);
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}
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static inline void armv7_stop_pmnc(void)
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{
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armv7_pmnc_write(armv7_pmnc_read() & ~PMNC_E);
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}
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/*
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* CPU counters' IRQ handler (one IRQ per CPU)
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*/
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static irqreturn_t armv7_pmnc_interrupt(int irq, void *arg)
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{
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struct pt_regs *regs = get_irq_regs();
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unsigned int cnt;
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u32 flags;
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/*
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* Stop IRQ generation
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*/
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armv7_stop_pmnc();
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/*
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* Get and reset overflow status flags
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*/
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flags = armv7_pmnc_getreset_flags();
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/*
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* Cycle counter
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*/
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if (flags & FLAG_C) {
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u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), CCNT);
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armv7_pmnc_reset_counter(CCNT);
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oprofile_add_sample(regs, cpu_cnt);
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}
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/*
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* PMNC counters 0:3
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*/
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for (cnt = CNT0; cnt < CNTMAX; cnt++) {
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if (flags & (1 << (cnt - CNT0))) {
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u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt);
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armv7_pmnc_reset_counter(cnt);
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oprofile_add_sample(regs, cpu_cnt);
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}
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}
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/*
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* Allow IRQ generation
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*/
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armv7_start_pmnc();
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return IRQ_HANDLED;
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}
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int armv7_request_interrupts(const int *irqs, int nr)
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{
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unsigned int i;
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int ret = 0;
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for (i = 0; i < nr; i++) {
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ret = request_irq(irqs[i], armv7_pmnc_interrupt,
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IRQF_DISABLED, "CP15 PMNC", NULL);
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if (ret != 0) {
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printk(KERN_ERR "oprofile: unable to request IRQ%u"
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" for ARMv7\n",
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irqs[i]);
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break;
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}
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}
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if (i != nr)
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while (i-- != 0)
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free_irq(irqs[i], NULL);
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return ret;
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}
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void armv7_release_interrupts(const int *irqs, int nr)
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{
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unsigned int i;
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for (i = 0; i < nr; i++)
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free_irq(irqs[i], NULL);
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}
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#ifdef DEBUG
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static void armv7_pmnc_dump_regs(void)
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{
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u32 val;
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unsigned int cnt;
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printk(KERN_INFO "PMNC registers dump:\n");
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asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
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printk(KERN_INFO "PMNC =0x%08x\n", val);
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asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
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printk(KERN_INFO "CNTENS=0x%08x\n", val);
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asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
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printk(KERN_INFO "INTENS=0x%08x\n", val);
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asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
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printk(KERN_INFO "FLAGS =0x%08x\n", val);
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asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
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printk(KERN_INFO "SELECT=0x%08x\n", val);
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asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
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printk(KERN_INFO "CCNT =0x%08x\n", val);
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for (cnt = CNT0; cnt < CNTMAX; cnt++) {
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armv7_pmnc_select_counter(cnt);
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asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
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printk(KERN_INFO "CNT[%d] count =0x%08x\n", cnt-CNT0, val);
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asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
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printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n", cnt-CNT0, val);
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}
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}
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#endif
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static const struct pmu_irqs *pmu_irqs;
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static void armv7_pmnc_stop(void)
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{
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#ifdef DEBUG
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armv7_pmnc_dump_regs();
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#endif
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armv7_stop_pmnc();
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armv7_release_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs);
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release_pmu(pmu_irqs);
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pmu_irqs = NULL;
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}
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static int armv7_pmnc_start(void)
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{
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int ret;
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pmu_irqs = reserve_pmu();
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if (IS_ERR(pmu_irqs))
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return PTR_ERR(pmu_irqs);
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#ifdef DEBUG
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armv7_pmnc_dump_regs();
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#endif
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ret = armv7_request_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs);
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if (ret >= 0) {
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armv7_start_pmnc();
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} else {
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release_pmu(pmu_irqs);
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pmu_irqs = NULL;
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}
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return ret;
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}
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static int armv7_detect_pmnc(void)
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{
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return 0;
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}
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struct op_arm_model_spec op_armv7_spec = {
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.init = armv7_detect_pmnc,
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.num_counters = 5,
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.setup_ctrs = armv7_setup_pmnc,
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.start = armv7_pmnc_start,
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.stop = armv7_pmnc_stop,
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.name = "arm/armv7",
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};
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