mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
a16942e630
Going through full htc tx path for htt tx is a waste of resources. By skipping it it's possible to easily submit scatter-gather to the pci hif for reduced host cpu load and improved performance. The new approach uses dma pool to store the following metadata for each tx request: * msdu fragment list * htc header * htt tx command The htt tx command contains a msdu prefetch. Instead of copying it original mapped msdu address is used to submit a second scatter-gather item to hif to make a complete htt tx command. The htt tx command itself hands over dma mapped pointers to msdus and completion of the command itself doesn't mean the frame has been sent and can be unmapped/freed. This is why htc tx completion is skipped for htt tx as all tx related resources are freed upon htt tx completion indication event (which also implicitly means htt tx command itself was completed). Since now each htt tx request effectively consists of 2 copy engine items CE_HTT_H2T_MSG_SRC_NENTRIES is updated to allow maximum of TARGET_10X_NUM_MSDU_DESC msdus being queued. This keeps the tx path resource management simple. Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
440 lines
14 KiB
C
440 lines
14 KiB
C
/*
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* Copyright (c) 2005-2011 Atheros Communications Inc.
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* Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _CE_H_
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#define _CE_H_
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#include "hif.h"
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/* Maximum number of Copy Engine's supported */
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#define CE_COUNT_MAX 8
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#define CE_HTT_H2T_MSG_SRC_NENTRIES 4096
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/* Descriptor rings must be aligned to this boundary */
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#define CE_DESC_RING_ALIGN 8
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#define CE_SEND_FLAG_GATHER 0x00010000
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/*
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* Copy Engine support: low-level Target-side Copy Engine API.
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* This is a hardware access layer used by code that understands
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* how to use copy engines.
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*/
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struct ath10k_ce_pipe;
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#define CE_DESC_FLAGS_GATHER (1 << 0)
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#define CE_DESC_FLAGS_BYTE_SWAP (1 << 1)
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#define CE_DESC_FLAGS_META_DATA_MASK 0xFFFC
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#define CE_DESC_FLAGS_META_DATA_LSB 3
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struct ce_desc {
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__le32 addr;
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__le16 nbytes;
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__le16 flags; /* %CE_DESC_FLAGS_ */
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};
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struct ath10k_ce_ring {
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/* Number of entries in this ring; must be power of 2 */
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unsigned int nentries;
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unsigned int nentries_mask;
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/*
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* For dest ring, this is the next index to be processed
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* by software after it was/is received into.
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*
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* For src ring, this is the last descriptor that was sent
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* and completion processed by software.
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*
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* Regardless of src or dest ring, this is an invariant
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* (modulo ring size):
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* write index >= read index >= sw_index
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*/
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unsigned int sw_index;
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/* cached copy */
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unsigned int write_index;
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/*
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* For src ring, this is the next index not yet processed by HW.
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* This is a cached copy of the real HW index (read index), used
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* for avoiding reading the HW index register more often than
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* necessary.
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* This extends the invariant:
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* write index >= read index >= hw_index >= sw_index
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*
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* For dest ring, this is currently unused.
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*/
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/* cached copy */
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unsigned int hw_index;
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/* Start of DMA-coherent area reserved for descriptors */
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/* Host address space */
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void *base_addr_owner_space_unaligned;
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/* CE address space */
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u32 base_addr_ce_space_unaligned;
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/*
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* Actual start of descriptors.
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* Aligned to descriptor-size boundary.
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* Points into reserved DMA-coherent area, above.
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*/
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/* Host address space */
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void *base_addr_owner_space;
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/* CE address space */
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u32 base_addr_ce_space;
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/*
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* Start of shadow copy of descriptors, within regular memory.
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* Aligned to descriptor-size boundary.
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*/
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void *shadow_base_unaligned;
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struct ce_desc *shadow_base;
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void **per_transfer_context;
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};
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struct ath10k_ce_pipe {
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struct ath10k *ar;
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unsigned int id;
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unsigned int attr_flags;
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u32 ctrl_addr;
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void (*send_cb)(struct ath10k_ce_pipe *);
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void (*recv_cb)(struct ath10k_ce_pipe *);
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unsigned int src_sz_max;
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struct ath10k_ce_ring *src_ring;
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struct ath10k_ce_ring *dest_ring;
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};
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/* Copy Engine settable attributes */
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struct ce_attr;
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/*==================Send====================*/
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/* ath10k_ce_send flags */
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#define CE_SEND_FLAG_BYTE_SWAP 1
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/*
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* Queue a source buffer to be sent to an anonymous destination buffer.
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* ce - which copy engine to use
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* buffer - address of buffer
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* nbytes - number of bytes to send
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* transfer_id - arbitrary ID; reflected to destination
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* flags - CE_SEND_FLAG_* values
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* Returns 0 on success; otherwise an error status.
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*
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* Note: If no flags are specified, use CE's default data swap mode.
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*
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* Implementation note: pushes 1 buffer to Source ring
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*/
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int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
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void *per_transfer_send_context,
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u32 buffer,
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unsigned int nbytes,
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/* 14 bits */
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unsigned int transfer_id,
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unsigned int flags);
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int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
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void *per_transfer_context,
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u32 buffer,
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unsigned int nbytes,
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unsigned int transfer_id,
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unsigned int flags);
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void ath10k_ce_send_cb_register(struct ath10k_ce_pipe *ce_state,
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void (*send_cb)(struct ath10k_ce_pipe *),
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int disable_interrupts);
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int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe);
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/*==================Recv=======================*/
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/*
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* Make a buffer available to receive. The buffer must be at least of a
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* minimal size appropriate for this copy engine (src_sz_max attribute).
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* ce - which copy engine to use
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* per_transfer_recv_context - context passed back to caller's recv_cb
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* buffer - address of buffer in CE space
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* Returns 0 on success; otherwise an error status.
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*
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* Implemenation note: Pushes a buffer to Dest ring.
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*/
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int ath10k_ce_recv_buf_enqueue(struct ath10k_ce_pipe *ce_state,
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void *per_transfer_recv_context,
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u32 buffer);
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void ath10k_ce_recv_cb_register(struct ath10k_ce_pipe *ce_state,
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void (*recv_cb)(struct ath10k_ce_pipe *));
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/* recv flags */
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/* Data is byte-swapped */
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#define CE_RECV_FLAG_SWAPPED 1
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/*
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* Supply data for the next completed unprocessed receive descriptor.
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* Pops buffer from Dest ring.
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*/
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int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
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void **per_transfer_contextp,
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u32 *bufferp,
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unsigned int *nbytesp,
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unsigned int *transfer_idp,
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unsigned int *flagsp);
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/*
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* Supply data for the next completed unprocessed send descriptor.
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* Pops 1 completed send buffer from Source ring.
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*/
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int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
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void **per_transfer_contextp,
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u32 *bufferp,
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unsigned int *nbytesp,
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unsigned int *transfer_idp);
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/*==================CE Engine Initialization=======================*/
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/* Initialize an instance of a CE */
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struct ath10k_ce_pipe *ath10k_ce_init(struct ath10k *ar,
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unsigned int ce_id,
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const struct ce_attr *attr);
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/*==================CE Engine Shutdown=======================*/
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/*
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* Support clean shutdown by allowing the caller to revoke
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* receive buffers. Target DMA must be stopped before using
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* this API.
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*/
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int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
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void **per_transfer_contextp,
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u32 *bufferp);
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/*
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* Support clean shutdown by allowing the caller to cancel
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* pending sends. Target DMA must be stopped before using
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* this API.
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*/
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int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
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void **per_transfer_contextp,
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u32 *bufferp,
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unsigned int *nbytesp,
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unsigned int *transfer_idp);
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void ath10k_ce_deinit(struct ath10k_ce_pipe *ce_state);
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/*==================CE Interrupt Handlers====================*/
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void ath10k_ce_per_engine_service_any(struct ath10k *ar);
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void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id);
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int ath10k_ce_disable_interrupts(struct ath10k *ar);
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/* ce_attr.flags values */
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/* Use NonSnooping PCIe accesses? */
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#define CE_ATTR_NO_SNOOP 1
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/* Byte swap data words */
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#define CE_ATTR_BYTE_SWAP_DATA 2
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/* Swizzle descriptors? */
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#define CE_ATTR_SWIZZLE_DESCRIPTORS 4
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/* no interrupt on copy completion */
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#define CE_ATTR_DIS_INTR 8
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/* Attributes of an instance of a Copy Engine */
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struct ce_attr {
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/* CE_ATTR_* values */
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unsigned int flags;
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/* #entries in source ring - Must be a power of 2 */
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unsigned int src_nentries;
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/*
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* Max source send size for this CE.
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* This is also the minimum size of a destination buffer.
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*/
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unsigned int src_sz_max;
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/* #entries in destination ring - Must be a power of 2 */
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unsigned int dest_nentries;
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};
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#define SR_BA_ADDRESS 0x0000
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#define SR_SIZE_ADDRESS 0x0004
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#define DR_BA_ADDRESS 0x0008
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#define DR_SIZE_ADDRESS 0x000c
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#define CE_CMD_ADDRESS 0x0018
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#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB 17
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#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17
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#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000
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#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \
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(((0 | (x)) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \
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CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MSB 16
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_GET(x) \
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(((x) & CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) >> \
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CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \
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(((0 | (x)) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \
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CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
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#define CE_CTRL1_DMAX_LENGTH_MSB 15
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#define CE_CTRL1_DMAX_LENGTH_LSB 0
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#define CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff
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#define CE_CTRL1_DMAX_LENGTH_GET(x) \
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(((x) & CE_CTRL1_DMAX_LENGTH_MASK) >> CE_CTRL1_DMAX_LENGTH_LSB)
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#define CE_CTRL1_DMAX_LENGTH_SET(x) \
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(((0 | (x)) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)
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#define CE_CTRL1_ADDRESS 0x0010
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#define CE_CTRL1_HW_MASK 0x0007ffff
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#define CE_CTRL1_SW_MASK 0x0007ffff
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#define CE_CTRL1_HW_WRITE_MASK 0x00000000
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#define CE_CTRL1_SW_WRITE_MASK 0x0007ffff
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#define CE_CTRL1_RSTMASK 0xffffffff
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#define CE_CTRL1_RESET 0x00000080
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#define CE_CMD_HALT_STATUS_MSB 3
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#define CE_CMD_HALT_STATUS_LSB 3
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#define CE_CMD_HALT_STATUS_MASK 0x00000008
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#define CE_CMD_HALT_STATUS_GET(x) \
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(((x) & CE_CMD_HALT_STATUS_MASK) >> CE_CMD_HALT_STATUS_LSB)
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#define CE_CMD_HALT_STATUS_SET(x) \
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(((0 | (x)) << CE_CMD_HALT_STATUS_LSB) & CE_CMD_HALT_STATUS_MASK)
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#define CE_CMD_HALT_STATUS_RESET 0
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#define CE_CMD_HALT_MSB 0
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#define CE_CMD_HALT_MASK 0x00000001
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#define HOST_IE_COPY_COMPLETE_MSB 0
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#define HOST_IE_COPY_COMPLETE_LSB 0
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#define HOST_IE_COPY_COMPLETE_MASK 0x00000001
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#define HOST_IE_COPY_COMPLETE_GET(x) \
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(((x) & HOST_IE_COPY_COMPLETE_MASK) >> HOST_IE_COPY_COMPLETE_LSB)
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#define HOST_IE_COPY_COMPLETE_SET(x) \
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(((0 | (x)) << HOST_IE_COPY_COMPLETE_LSB) & HOST_IE_COPY_COMPLETE_MASK)
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#define HOST_IE_COPY_COMPLETE_RESET 0
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#define HOST_IE_ADDRESS 0x002c
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#define HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010
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#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008
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#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004
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#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002
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#define HOST_IS_COPY_COMPLETE_MASK 0x00000001
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#define HOST_IS_ADDRESS 0x0030
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#define MISC_IE_ADDRESS 0x0034
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#define MISC_IS_AXI_ERR_MASK 0x00000400
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#define MISC_IS_DST_ADDR_ERR_MASK 0x00000200
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#define MISC_IS_SRC_LEN_ERR_MASK 0x00000100
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#define MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080
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#define MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040
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#define MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020
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#define MISC_IS_ADDRESS 0x0038
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#define SR_WR_INDEX_ADDRESS 0x003c
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#define DST_WR_INDEX_ADDRESS 0x0040
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#define CURRENT_SRRI_ADDRESS 0x0044
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#define CURRENT_DRRI_ADDRESS 0x0048
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#define SRC_WATERMARK_LOW_MSB 31
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#define SRC_WATERMARK_LOW_LSB 16
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#define SRC_WATERMARK_LOW_MASK 0xffff0000
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#define SRC_WATERMARK_LOW_GET(x) \
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(((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB)
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#define SRC_WATERMARK_LOW_SET(x) \
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(((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)
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#define SRC_WATERMARK_LOW_RESET 0
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#define SRC_WATERMARK_HIGH_MSB 15
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#define SRC_WATERMARK_HIGH_LSB 0
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#define SRC_WATERMARK_HIGH_MASK 0x0000ffff
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#define SRC_WATERMARK_HIGH_GET(x) \
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(((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB)
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#define SRC_WATERMARK_HIGH_SET(x) \
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(((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)
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#define SRC_WATERMARK_HIGH_RESET 0
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#define SRC_WATERMARK_ADDRESS 0x004c
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#define DST_WATERMARK_LOW_LSB 16
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#define DST_WATERMARK_LOW_MASK 0xffff0000
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#define DST_WATERMARK_LOW_SET(x) \
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(((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)
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#define DST_WATERMARK_LOW_RESET 0
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#define DST_WATERMARK_HIGH_MSB 15
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#define DST_WATERMARK_HIGH_LSB 0
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#define DST_WATERMARK_HIGH_MASK 0x0000ffff
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#define DST_WATERMARK_HIGH_GET(x) \
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(((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB)
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#define DST_WATERMARK_HIGH_SET(x) \
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(((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)
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#define DST_WATERMARK_HIGH_RESET 0
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#define DST_WATERMARK_ADDRESS 0x0050
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static inline u32 ath10k_ce_base_address(unsigned int ce_id)
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{
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return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;
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}
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#define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \
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HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \
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HOST_IS_DST_RING_LOW_WATERMARK_MASK | \
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HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
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#define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \
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MISC_IS_DST_ADDR_ERR_MASK | \
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MISC_IS_SRC_LEN_ERR_MASK | \
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MISC_IS_DST_MAX_LEN_VIO_MASK | \
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MISC_IS_DST_RING_OVERFLOW_MASK | \
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MISC_IS_SRC_RING_OVERFLOW_MASK)
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#define CE_SRC_RING_TO_DESC(baddr, idx) \
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(&(((struct ce_desc *)baddr)[idx]))
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#define CE_DEST_RING_TO_DESC(baddr, idx) \
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(&(((struct ce_desc *)baddr)[idx]))
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/* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */
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#define CE_RING_DELTA(nentries_mask, fromidx, toidx) \
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(((int)(toidx)-(int)(fromidx)) & (nentries_mask))
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#define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
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#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8
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#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
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#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \
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(((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
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CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
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#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
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#define CE_INTERRUPT_SUMMARY(ar) \
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CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \
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ath10k_pci_read32((ar), CE_WRAPPER_BASE_ADDRESS + \
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CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS))
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#endif /* _CE_H_ */
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