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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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539d5c48a4
Set cpu_alert0 temperature to 85°C instead of 850°C.
Fixes: 32a5d2d170 ("ARM: dts: sun5i: Add cpu thermal zones to dtsi")
Signed-off-by: Hugo Grostabussiat <bonstra@bonstra.fr.eu.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
376 lines
9.1 KiB
Plaintext
376 lines
9.1 KiB
Plaintext
/*
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* Copyright 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include "sun5i.dtsi"
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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interrupt-parent = <&intc>;
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chosen {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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framebuffer@0 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0";
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clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>,
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<&tcon_ch0_clk>, <&dram_gates 26>;
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status = "disabled";
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};
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};
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thermal-zones {
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cpu_thermal {
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/* milliseconds */
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&rtp>;
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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trips {
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cpu_alert0: cpu_alert0 {
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/* milliCelsius */
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu_crit {
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/* milliCelsius */
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temperature = <100000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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clocks {
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ahb_gates: clk@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun5i-a13-ahb-gates-clk";
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reg = <0x01c20060 0x8>;
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clocks = <&ahb>;
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clock-indices = <0>, <1>,
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<2>, <5>, <6>,
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<7>, <8>, <9>,
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<10>, <13>,
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<14>, <20>,
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<21>, <22>,
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<28>, <32>, <34>,
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<36>, <40>, <44>,
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<46>, <51>,
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<52>;
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clock-output-names = "ahb_usbotg", "ahb_ehci",
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"ahb_ohci", "ahb_ss", "ahb_dma",
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"ahb_bist", "ahb_mmc0", "ahb_mmc1",
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"ahb_mmc2", "ahb_nand",
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"ahb_sdram", "ahb_spi0",
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"ahb_spi1", "ahb_spi2",
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"ahb_stimer", "ahb_ve", "ahb_tve",
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"ahb_lcd", "ahb_csi", "ahb_de_be",
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"ahb_de_fe", "ahb_iep",
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"ahb_mali400";
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};
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apb0_gates: clk@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun5i-a13-apb0-gates-clk";
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reg = <0x01c20068 0x4>;
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clocks = <&apb0>;
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clock-indices = <0>, <5>,
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<6>;
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clock-output-names = "apb0_codec", "apb0_pio",
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"apb0_ir";
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};
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apb1_gates: clk@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun5i-a13-apb1-gates-clk";
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reg = <0x01c2006c 0x4>;
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clocks = <&apb1>;
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clock-indices = <0>, <1>,
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<2>, <17>,
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<19>;
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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"apb1_i2c2", "apb1_uart1",
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"apb1_uart3";
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};
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dram_gates: clk@01c20100 {
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#clock-cells = <1>;
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compatible = "allwinner,sun5i-a13-dram-gates-clk",
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"allwinner,sun4i-a10-gates-clk";
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reg = <0x01c20100 0x4>;
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clocks = <&pll5 0>;
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clock-indices = <0>,
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<1>,
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<25>,
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<26>,
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<29>,
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<31>;
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clock-output-names = "dram_ve",
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"dram_csi",
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"dram_de_fe",
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"dram_de_be",
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"dram_ace",
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"dram_iep";
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};
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de_be_clk: clk@01c20104 {
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#clock-cells = <0>;
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#reset-cells = <0>;
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compatible = "allwinner,sun4i-a10-display-clk";
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reg = <0x01c20104 0x4>;
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clocks = <&pll3>, <&pll7>, <&pll5 1>;
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clock-output-names = "de-be";
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};
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de_fe_clk: clk@01c2010c {
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#clock-cells = <0>;
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#reset-cells = <0>;
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compatible = "allwinner,sun4i-a10-display-clk";
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reg = <0x01c2010c 0x4>;
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clocks = <&pll3>, <&pll7>, <&pll5 1>;
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clock-output-names = "de-fe";
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};
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tcon_ch0_clk: clk@01c20118 {
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#clock-cells = <0>;
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#reset-cells = <1>;
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compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
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reg = <0x01c20118 0x4>;
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clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
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clock-output-names = "tcon-ch0-sclk";
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};
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tcon_ch1_clk: clk@01c2012c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
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reg = <0x01c2012c 0x4>;
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clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
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clock-output-names = "tcon-ch1-sclk";
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};
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};
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display-engine {
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compatible = "allwinner,sun5i-a13-display-engine";
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allwinner,pipelines = <&fe0>;
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};
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soc@01c00000 {
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tcon0: lcd-controller@01c0c000 {
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compatible = "allwinner,sun5i-a13-tcon";
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reg = <0x01c0c000 0x1000>;
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interrupts = <44>;
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resets = <&tcon_ch0_clk 1>;
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reset-names = "lcd";
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clocks = <&ahb_gates 36>,
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<&tcon_ch0_clk>,
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<&tcon_ch1_clk>;
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clock-names = "ahb",
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"tcon-ch0",
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"tcon-ch1";
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clock-output-names = "tcon-pixel-clock";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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tcon0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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tcon0_in_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_out_tcon0>;
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};
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};
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tcon0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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};
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};
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pwm: pwm@01c20e00 {
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compatible = "allwinner,sun5i-a13-pwm";
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reg = <0x01c20e00 0xc>;
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clocks = <&osc24M>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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fe0: display-frontend@01e00000 {
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compatible = "allwinner,sun5i-a13-display-frontend";
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reg = <0x01e00000 0x20000>;
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interrupts = <47>;
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clocks = <&ahb_gates 46>, <&de_fe_clk>,
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<&dram_gates 25>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&de_fe_clk>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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fe0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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fe0_out_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_in_fe0>;
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};
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};
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};
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};
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be0: display-backend@01e60000 {
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compatible = "allwinner,sun5i-a13-display-backend";
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reg = <0x01e60000 0x10000>;
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clocks = <&ahb_gates 44>, <&de_be_clk>,
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<&dram_gates 26>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&de_be_clk>;
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status = "disabled";
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assigned-clocks = <&de_be_clk>;
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assigned-clock-rates = <300000000>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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be0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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be0_in_fe0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&fe0_out_be0>;
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};
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};
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be0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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be0_out_tcon0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&tcon0_in_be0>;
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};
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};
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};
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};
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};
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};
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&cpu0 {
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clock-latency = <244144>; /* 8 32k periods */
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operating-points = <
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/* kHz uV */
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1008000 1400000
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912000 1350000
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864000 1300000
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624000 1200000
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576000 1200000
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432000 1200000
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>;
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#cooling-cells = <2>;
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cooling-min-level = <0>;
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cooling-max-level = <5>;
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};
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&pio {
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compatible = "allwinner,sun5i-a13-pinctrl";
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lcd_rgb666_pins: lcd_rgb666@0 {
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allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
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"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
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"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
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"PD24", "PD25", "PD26", "PD27";
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allwinner,function = "lcd0";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart1_pins_a: uart1@0 {
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allwinner,pins = "PE10", "PE11";
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allwinner,function = "uart1";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart1_pins_b: uart1@1 {
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allwinner,pins = "PG3", "PG4";
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allwinner,function = "uart1";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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};
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