Chris Wilson 1a74934b0e drm/i915/gem: Flush the pwrite through the chipset before signaling ... Before we signal the fence to indicate completion, ensure the pwrite through the indirect GGTT is coherent (as best as we know) in memory. Any listeners to the fence may start immediately and sample from the backing store prior to the writes being posted, thus seeing stale data. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191206105527.1130413-1-chris@chris-wilson.co.uk		2019-12-06 11:39:12 +00:00
..
drm	drm/i915/gem: Flush the pwrite through the chipset before signaling	2019-12-06 11:39:12 +00:00
host1x	gpu: host1x: Unconditionally select IOMMU_IOVA	2019-11-01 10:49:17 +01:00
ipu-v3
vga
Makefile