mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 10:35:04 +07:00
d816b3cc77
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
55 lines
1.0 KiB
Plaintext
55 lines
1.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Device Tree Include file for Marvell 98dx4521 family SoC
|
|
*
|
|
* Copyright (C) 2016 Allied Telesis Labs
|
|
*
|
|
* Contains definitions specific to the 98dx4521 SoC that are not
|
|
* common to all Armada XP SoCs.
|
|
*/
|
|
|
|
#include "armada-xp-98dx3236.dtsi"
|
|
|
|
/ {
|
|
model = "Marvell 98DX4251 SoC";
|
|
compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
|
|
|
|
cpus {
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "marvell,sheeva-v7";
|
|
reg = <1>;
|
|
clocks = <&cpuclk 1>;
|
|
clock-latency = <1000000>;
|
|
};
|
|
};
|
|
|
|
soc {
|
|
internal-regs {
|
|
resume@20980 {
|
|
compatible = "marvell,98dx3336-resume-ctrl";
|
|
reg = <0x20980 0x10>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&sdio {
|
|
status = "okay";
|
|
};
|
|
|
|
&pinctrl {
|
|
compatible = "marvell,98dx4251-pinctrl";
|
|
|
|
sdio_pins: sdio-pins {
|
|
marvell,pins = "mpp5", "mpp6", "mpp7",
|
|
"mpp8", "mpp9", "mpp10";
|
|
marvell,function = "sd0";
|
|
};
|
|
};
|
|
|
|
&pp0 {
|
|
compatible = "marvell,prestera-98dx4251";
|
|
interrupts = <33>, <34>, <35>, <36>;
|
|
};
|