Eugeniy Paltsev fbd1cec570 ARC: [plat-axs103]: Set initial core pll output frequency ... Set initial core pll output frequency specified in device tree to 100MHz for SMP configuration and 90MHz for UP configuration. It will be applied at the core pll driver probing. Update platform quirk for decreasing core frequency for quad core configuration. Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2017-12-20 12:41:45 -08:00
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dts	ARC: [plat-axs103]: Set initial core pll output frequency	2017-12-20 12:41:45 -08:00
.gitignore	.gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignore	2017-11-08 11:20:24 -06:00
Makefile	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00