mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 18:40:53 +07:00
01824a5767
Commit f4d809ec55b6 ("ARM: dts: Fix gpmc timings for omap 2430sdp")
added GPMC timings for 2430sdp. This however broke the Ethernet
for some versions of u-boot using a different L3 clock frequency:
set_gpmc_timing_reg: GPMC error! CS5: cs_rd_off: 233 ns, 39 ticks > 31
omap-gpmc 6e000000.gpmc: failed to set gpmc timings for: ethernet
This is because the smsc91x timings from 1.1.4 u-boot overflow the
GPMC registers when booted with 1.1.3 version of u-boot.
Let's fix this issue by using the better timings from u-boot 1.1.3
as they also work on 1.1.4 and are faster.
Note that so far the attempts over the years to calculate the GPMC
timings on the SDP boards have failed probably because of the
unknown latencies added by the FPGA on the debug boards.
Reported-by: Nishanth Menon <nm@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
74 lines
1.6 KiB
Plaintext
74 lines
1.6 KiB
Plaintext
/*
|
|
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
/dts-v1/;
|
|
|
|
#include "omap2430.dtsi"
|
|
|
|
/ {
|
|
model = "TI OMAP2430 SDP";
|
|
compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2";
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0x80000000 0x8000000>; /* 128 MB */
|
|
};
|
|
};
|
|
|
|
&i2c2 {
|
|
clock-frequency = <100000>;
|
|
|
|
twl: twl@48 {
|
|
reg = <0x48>;
|
|
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
|
|
};
|
|
};
|
|
|
|
#include "twl4030.dtsi"
|
|
|
|
&mmc1 {
|
|
vmmc-supply = <&vmmc1>;
|
|
bus-width = <4>;
|
|
};
|
|
|
|
&gpmc {
|
|
ranges = <5 0 0x08000000 0x01000000>;
|
|
ethernet@gpmc {
|
|
compatible = "smsc,lan91c94";
|
|
interrupt-parent = <&gpio5>;
|
|
interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */
|
|
reg = <5 0x300 0xf>;
|
|
bank-width = <2>;
|
|
gpmc,sync-clk-ps = <0>;
|
|
gpmc,mux-add-data = <2>;
|
|
gpmc,device-width = <1>;
|
|
gpmc,cycle2cycle-samecsen = <1>;
|
|
gpmc,cycle2cycle-diffcsen = <1>;
|
|
gpmc,cs-on-ns = <6>;
|
|
gpmc,cs-rd-off-ns = <187>;
|
|
gpmc,cs-wr-off-ns = <187>;
|
|
gpmc,adv-on-ns = <18>;
|
|
gpmc,adv-rd-off-ns = <48>;
|
|
gpmc,adv-wr-off-ns = <48>;
|
|
gpmc,oe-on-ns = <60>;
|
|
gpmc,oe-off-ns = <169>;
|
|
gpmc,we-on-ns = <66>;
|
|
gpmc,we-off-ns = <169>;
|
|
gpmc,rd-cycle-ns = <187>;
|
|
gpmc,wr-cycle-ns = <187>;
|
|
gpmc,access-ns = <187>;
|
|
gpmc,page-burst-access-ns = <24>;
|
|
gpmc,bus-turnaround-ns = <24>;
|
|
gpmc,cycle2cycle-delay-ns = <24>;
|
|
gpmc,wait-monitoring-ns = <0>;
|
|
gpmc,clk-activation-ns = <0>;
|
|
gpmc,wr-data-mux-bus-ns = <0>;
|
|
gpmc,wr-access-ns = <0>;
|
|
};
|
|
};
|
|
|