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1a1a36d72e
This allows gclk to determine audio_pll rate and set the parent rate accordingly. However, there are multiple children clocks that could technically change the rate of audio_pll (via gck). With the rate locking, the first consumer to enable the clock will be the one definitely setting the rate of the clock. Since audio IPs are most likely to request the same rate, we enforce that the only clks able to modify gck rate are those of audio IPs. To remain consistent, we deny other clocks to be children of audio_pll. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
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| .. | ||
| clk-audio-pll.c | ||
| clk-generated.c | ||
| clk-h32mx.c | ||
| clk-main.c | ||
| clk-master.c | ||
| clk-peripheral.c | ||
| clk-pll.c | ||
| clk-plldiv.c | ||
| clk-programmable.c | ||
| clk-slow.c | ||
| clk-smd.c | ||
| clk-system.c | ||
| clk-usb.c | ||
| clk-utmi.c | ||
| Makefile | ||
| pmc.c | ||
| pmc.h | ||
| sckc.c | ||