mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 18:17:49 +07:00
08e237fa56
Monitored cached line may not wake up from mwait on certain Goldmont based CPUs. This patch will avoid calling current_set_polling_and_test() and thereby not set the TIF_ flag. The result is that we'll always send IPIs for wakeups. Signed-off-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Arjan van de Ven <arjan@linux.intel.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Len Brown <lenb@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1468867270-18493-1-git-send-email-jacob.jun.pan@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
115 lines
3.5 KiB
C
115 lines
3.5 KiB
C
#ifndef _ASM_X86_MWAIT_H
|
|
#define _ASM_X86_MWAIT_H
|
|
|
|
#include <linux/sched.h>
|
|
|
|
#include <asm/cpufeature.h>
|
|
|
|
#define MWAIT_SUBSTATE_MASK 0xf
|
|
#define MWAIT_CSTATE_MASK 0xf
|
|
#define MWAIT_SUBSTATE_SIZE 4
|
|
#define MWAIT_HINT2CSTATE(hint) (((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK)
|
|
#define MWAIT_HINT2SUBSTATE(hint) ((hint) & MWAIT_CSTATE_MASK)
|
|
|
|
#define CPUID_MWAIT_LEAF 5
|
|
#define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1
|
|
#define CPUID5_ECX_INTERRUPT_BREAK 0x2
|
|
|
|
#define MWAIT_ECX_INTERRUPT_BREAK 0x1
|
|
#define MWAITX_ECX_TIMER_ENABLE BIT(1)
|
|
#define MWAITX_MAX_LOOPS ((u32)-1)
|
|
#define MWAITX_DISABLE_CSTATES 0xf
|
|
|
|
static inline void __monitor(const void *eax, unsigned long ecx,
|
|
unsigned long edx)
|
|
{
|
|
/* "monitor %eax, %ecx, %edx;" */
|
|
asm volatile(".byte 0x0f, 0x01, 0xc8;"
|
|
:: "a" (eax), "c" (ecx), "d"(edx));
|
|
}
|
|
|
|
static inline void __monitorx(const void *eax, unsigned long ecx,
|
|
unsigned long edx)
|
|
{
|
|
/* "monitorx %eax, %ecx, %edx;" */
|
|
asm volatile(".byte 0x0f, 0x01, 0xfa;"
|
|
:: "a" (eax), "c" (ecx), "d"(edx));
|
|
}
|
|
|
|
static inline void __mwait(unsigned long eax, unsigned long ecx)
|
|
{
|
|
/* "mwait %eax, %ecx;" */
|
|
asm volatile(".byte 0x0f, 0x01, 0xc9;"
|
|
:: "a" (eax), "c" (ecx));
|
|
}
|
|
|
|
/*
|
|
* MWAITX allows for a timer expiration to get the core out a wait state in
|
|
* addition to the default MWAIT exit condition of a store appearing at a
|
|
* monitored virtual address.
|
|
*
|
|
* Registers:
|
|
*
|
|
* MWAITX ECX[1]: enable timer if set
|
|
* MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks. The software P0
|
|
* frequency is the same as the TSC frequency.
|
|
*
|
|
* Below is a comparison between MWAIT and MWAITX on AMD processors:
|
|
*
|
|
* MWAIT MWAITX
|
|
* opcode 0f 01 c9 | 0f 01 fb
|
|
* ECX[0] value of RFLAGS.IF seen by instruction
|
|
* ECX[1] unused/#GP if set | enable timer if set
|
|
* ECX[31:2] unused/#GP if set
|
|
* EAX unused (reserve for hint)
|
|
* EBX[31:0] unused | max wait time (P0 clocks)
|
|
*
|
|
* MONITOR MONITORX
|
|
* opcode 0f 01 c8 | 0f 01 fa
|
|
* EAX (logical) address to monitor
|
|
* ECX #GP if not zero
|
|
*/
|
|
static inline void __mwaitx(unsigned long eax, unsigned long ebx,
|
|
unsigned long ecx)
|
|
{
|
|
/* "mwaitx %eax, %ebx, %ecx;" */
|
|
asm volatile(".byte 0x0f, 0x01, 0xfb;"
|
|
:: "a" (eax), "b" (ebx), "c" (ecx));
|
|
}
|
|
|
|
static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
|
|
{
|
|
trace_hardirqs_on();
|
|
/* "mwait %eax, %ecx;" */
|
|
asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
|
|
:: "a" (eax), "c" (ecx));
|
|
}
|
|
|
|
/*
|
|
* This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
|
|
* which can obviate IPI to trigger checking of need_resched.
|
|
* We execute MONITOR against need_resched and enter optimized wait state
|
|
* through MWAIT. Whenever someone changes need_resched, we would be woken
|
|
* up from MWAIT (without an IPI).
|
|
*
|
|
* New with Core Duo processors, MWAIT can take some hints based on CPU
|
|
* capability.
|
|
*/
|
|
static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)
|
|
{
|
|
if (static_cpu_has_bug(X86_BUG_MONITOR) || !current_set_polling_and_test()) {
|
|
if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) {
|
|
mb();
|
|
clflush((void *)¤t_thread_info()->flags);
|
|
mb();
|
|
}
|
|
|
|
__monitor((void *)¤t_thread_info()->flags, 0, 0);
|
|
if (!need_resched())
|
|
__mwait(eax, ecx);
|
|
}
|
|
current_clr_polling();
|
|
}
|
|
|
|
#endif /* _ASM_X86_MWAIT_H */
|