mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 17:50:52 +07:00
128 lines
3.4 KiB
C
128 lines
3.4 KiB
C
#ifndef _X8664_TLBFLUSH_H
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#define _X8664_TLBFLUSH_H
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#include <linux/mm.h>
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#include <asm/processor.h>
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#define __flush_tlb() \
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do { \
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unsigned long tmpreg; \
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\
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__asm__ __volatile__( \
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"movq %%cr3, %0; # flush TLB \n" \
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"movq %0, %%cr3; \n" \
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: "=r" (tmpreg) \
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:: "memory"); \
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} while (0)
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/*
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* Global pages have to be flushed a bit differently. Not a real
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* performance problem because this does not happen often.
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*/
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#define __flush_tlb_global() \
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do { \
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unsigned long tmpreg, cr4, cr4_orig; \
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\
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__asm__ __volatile__( \
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"movq %%cr4, %2; # turn off PGE \n" \
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"movq %2, %1; \n" \
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"andq %3, %1; \n" \
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"movq %1, %%cr4; \n" \
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"movq %%cr3, %0; # flush TLB \n" \
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"movq %0, %%cr3; \n" \
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"movq %2, %%cr4; # turn PGE back on \n" \
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: "=&r" (tmpreg), "=&r" (cr4), "=&r" (cr4_orig) \
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: "i" (~X86_CR4_PGE) \
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: "memory"); \
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} while (0)
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extern unsigned long pgkern_mask;
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#define __flush_tlb_all() __flush_tlb_global()
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#define __flush_tlb_one(addr) \
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__asm__ __volatile__("invlpg %0": :"m" (*(char *) addr))
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/*
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* TLB flushing:
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*
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* - flush_tlb() flushes the current mm struct TLBs
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* - flush_tlb_all() flushes all processes TLBs
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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* - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
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*
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* x86-64 can only flush individual pages or full VMs. For a range flush
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* we always do the full VM. Might be worth trying if for a small
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* range a few INVLPGs in a row are a win.
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*/
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#ifndef CONFIG_SMP
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#define flush_tlb() __flush_tlb()
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#define flush_tlb_all() __flush_tlb_all()
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#define local_flush_tlb() __flush_tlb()
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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if (mm == current->active_mm)
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__flush_tlb();
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long addr)
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{
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if (vma->vm_mm == current->active_mm)
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__flush_tlb_one(addr);
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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if (vma->vm_mm == current->active_mm)
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__flush_tlb();
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}
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#else
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#include <asm/smp.h>
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#define local_flush_tlb() \
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__flush_tlb()
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extern void flush_tlb_all(void);
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extern void flush_tlb_current_task(void);
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extern void flush_tlb_mm(struct mm_struct *);
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extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
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#define flush_tlb() flush_tlb_current_task()
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static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
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{
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flush_tlb_mm(vma->vm_mm);
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}
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#define TLBSTATE_OK 1
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#define TLBSTATE_LAZY 2
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/* Roughly an IPI every 20MB with 4k pages for freeing page table
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ranges. Cost is about 42k of memory for each CPU. */
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#define ARCH_FREE_PTE_NR 5350
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#endif
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#define flush_tlb_kernel_range(start, end) flush_tlb_all()
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static inline void flush_tlb_pgtables(struct mm_struct *mm,
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unsigned long start, unsigned long end)
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{
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/* x86_64 does not keep any page table caches in a software TLB.
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The CPUs do in their hardware TLBs, but they are handled
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by the normal TLB flushing algorithms. */
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}
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#endif /* _X8664_TLBFLUSH_H */
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