mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 17:40:53 +07:00
9a0b26e6bc
- Move the slow path fallbacks to their own assembly files This makes them much easier to read and is needed for the next change. - Add CFI annotations for unwinding (XXX need review) - Remove constant case which can never happen with out of line spinlocks - Use patchable LOCK prefixes - Don't use lock sections anymore for inline code because they can't be expressed by the unwinder (this adds one taken jump to the lock fast path) Cc: jbeulich@novell.com Signed-off-by: Andi Kleen <ak@suse.de>
128 lines
2.9 KiB
C
128 lines
2.9 KiB
C
#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <asm/atomic.h>
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#include <asm/rwlock.h>
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#include <asm/page.h>
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/*
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* Your basic SMP spinlocks, allowing only a single CPU anywhere
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*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* We make no fairness assumptions. They have a cost.
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*
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* (the type definitions are in asm/spinlock_types.h)
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*/
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#define __raw_spin_is_locked(x) \
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(*(volatile signed int *)(&(x)->slock) <= 0)
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#define __raw_spin_lock_string \
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"\n1:\t" \
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LOCK_PREFIX " ; decl %0\n\t" \
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"js 2f\n" \
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LOCK_SECTION_START("") \
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"2:\t" \
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"rep;nop\n\t" \
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"cmpl $0,%0\n\t" \
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"jle 2b\n\t" \
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"jmp 1b\n" \
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LOCK_SECTION_END
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#define __raw_spin_lock_string_up \
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"\n\tdecl %0"
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#define __raw_spin_unlock_string \
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"movl $1,%0" \
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:"=m" (lock->slock) : : "memory"
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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asm volatile(__raw_spin_lock_string : "=m" (lock->slock) : : "memory");
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}
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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int oldval;
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__asm__ __volatile__(
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"xchgl %0,%1"
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:"=q" (oldval), "=m" (lock->slock)
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:"0" (0) : "memory");
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return oldval > 0;
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__(
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__raw_spin_unlock_string
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);
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}
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#define __raw_spin_unlock_wait(lock) \
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do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*
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* On x86, we implement read-write locks as a 32-bit counter
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* with the high bit (sign) being the "contended" bit.
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*/
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#define __raw_read_can_lock(x) ((int)(x)->lock > 0)
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#define __raw_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)
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static inline void __raw_read_lock(raw_rwlock_t *rw)
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{
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__build_read_lock(rw);
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}
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static inline void __raw_write_lock(raw_rwlock_t *rw)
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{
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__build_write_lock(rw);
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}
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static inline int __raw_read_trylock(raw_rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)lock;
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atomic_dec(count);
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if (atomic_read(count) >= 0)
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return 1;
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atomic_inc(count);
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return 0;
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}
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static inline int __raw_write_trylock(raw_rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)lock;
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if (atomic_sub_and_test(RW_LOCK_BIAS, count))
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return 1;
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atomic_add(RW_LOCK_BIAS, count);
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return 0;
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}
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static inline void __raw_read_unlock(raw_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX " ; incl %0" :"=m" (rw->lock) : : "memory");
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}
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static inline void __raw_write_unlock(raw_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX " ; addl $" RW_LOCK_BIAS_STR ",%0"
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: "=m" (rw->lock) : : "memory");
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}
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#endif /* __ASM_SPINLOCK_H */
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