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The micrel KSZ9031 phy has a optional clock pin (CLK125_NDO) which can be used as reference clock for the MAC unit. The clock signal must meet the RGMII requirements to ensure the correct data transmission between the MAC and the PHY. The KSZ9031 phy does not fulfill the duty cycle requirement if the phy is configured as slave. For a complete describtion look at the errata sheets: DS80000691D or DS80000692D. The errata sheet recommends to force the phy into master mode whenever there is a 1000Base-T link-up as work around. Only set the "micrel,force-master" property if you use the phy reference clock provided by CLK125_NDO pin as MAC reference clock in your application. Attenation, this workaround is only usable if the link partner can be configured to slave mode for 1000Base-T. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> [m.felsch@pengutronix.de: fix dt-binding documentation] [m.felsch@pengutronix.de: use already existing result var for read/write] [m.felsch@pengutronix.de: add error handling] [m.felsch@pengutronix.de: add more comments] Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
82 lines
2.8 KiB
Plaintext
82 lines
2.8 KiB
Plaintext
Micrel KSZ9021/KSZ9031 Gigabit Ethernet PHY
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Some boards require special tuning values, particularly when it comes
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to clock delays. You can specify clock delay values in the PHY OF
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device node. Deprecated, but still supported, these properties can
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also be added to an Ethernet OF device node.
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Note that these settings are applied after any phy-specific fixup from
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phy_fixup_list (see phy_init_hw() from drivers/net/phy/phy_device.c),
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and therefore may overwrite them.
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KSZ9021:
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All skew control options are specified in picoseconds. The minimum
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value is 0, the maximum value is 3000, and it is incremented by 200ps
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steps.
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Optional properties:
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- rxc-skew-ps : Skew control of RXC pad
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- rxdv-skew-ps : Skew control of RX CTL pad
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- txc-skew-ps : Skew control of TXC pad
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- txen-skew-ps : Skew control of TX CTL pad
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- rxd0-skew-ps : Skew control of RX data 0 pad
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- rxd1-skew-ps : Skew control of RX data 1 pad
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- rxd2-skew-ps : Skew control of RX data 2 pad
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- rxd3-skew-ps : Skew control of RX data 3 pad
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- txd0-skew-ps : Skew control of TX data 0 pad
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- txd1-skew-ps : Skew control of TX data 1 pad
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- txd2-skew-ps : Skew control of TX data 2 pad
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- txd3-skew-ps : Skew control of TX data 3 pad
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KSZ9031:
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All skew control options are specified in picoseconds. The minimum
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value is 0, and the maximum is property-dependent. The increment
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step is 60ps. The default value is the neutral setting, so setting
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rxc-skew-ps=<0> actually results in -900 picoseconds adjustment.
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Optional properties:
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Maximum value of 1860, default value 900:
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- rxc-skew-ps : Skew control of RX clock pad
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- txc-skew-ps : Skew control of TX clock pad
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Maximum value of 900, default value 420:
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- rxdv-skew-ps : Skew control of RX CTL pad
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- txen-skew-ps : Skew control of TX CTL pad
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- rxd0-skew-ps : Skew control of RX data 0 pad
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- rxd1-skew-ps : Skew control of RX data 1 pad
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- rxd2-skew-ps : Skew control of RX data 2 pad
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- rxd3-skew-ps : Skew control of RX data 3 pad
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- txd0-skew-ps : Skew control of TX data 0 pad
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- txd1-skew-ps : Skew control of TX data 1 pad
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- txd2-skew-ps : Skew control of TX data 2 pad
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- txd3-skew-ps : Skew control of TX data 3 pad
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- micrel,force-master:
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Boolean, force phy to master mode. Only set this option if the phy
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reference clock provided at CLK125_NDO pin is used as MAC reference
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clock because the clock jitter in slave mode is to high (errata#2).
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Attention: The link partner must be configurable as slave otherwise
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no link will be established.
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Examples:
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mdio {
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phy0: ethernet-phy@0 {
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rxc-skew-ps = <3000>;
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rxdv-skew-ps = <0>;
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txc-skew-ps = <3000>;
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txen-skew-ps = <0>;
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reg = <0>;
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};
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};
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ethernet@70000 {
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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