mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 11:47:02 +07:00
5573fe85c7
Add reset lines for ethernet controller on PXs3 SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
484 lines
14 KiB
C
484 lines
14 KiB
C
/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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struct uniphier_reset_data {
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unsigned int id;
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unsigned int reg;
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unsigned int bit;
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unsigned int flags;
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#define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
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};
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#define UNIPHIER_RESET_ID_END (unsigned int)(-1)
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#define UNIPHIER_RESET_END \
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{ .id = UNIPHIER_RESET_ID_END }
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#define UNIPHIER_RESET(_id, _reg, _bit) \
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{ \
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.id = (_id), \
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.reg = (_reg), \
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.bit = (_bit), \
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}
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#define UNIPHIER_RESETX(_id, _reg, _bit) \
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{ \
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.id = (_id), \
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.reg = (_reg), \
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.bit = (_bit), \
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.flags = UNIPHIER_RESET_ACTIVE_LOW, \
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}
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/* System reset data */
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static const struct uniphier_reset_data uniphier_ld4_sys_reset_data[] = {
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UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
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UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */
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UNIPHIER_RESET_END,
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};
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static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
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UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
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UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
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UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
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UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
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UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
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UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
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UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */
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UNIPHIER_RESET_END,
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};
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static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
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UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
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UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC) */
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UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (PCIe, USB3) */
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UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
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UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
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UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */
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UNIPHIER_RESET_END,
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};
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static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
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UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
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UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
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UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, RLE) */
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UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
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UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
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UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */
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UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */
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UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */
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UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */
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UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */
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UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */
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UNIPHIER_RESET(29, 0x2014, 8), /* SATA-PHY (active high) */
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UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */
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UNIPHIER_RESET_END,
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};
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static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
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UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
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UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
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UNIPHIER_RESETX(6, 0x200c, 6), /* Ether */
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UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC, MIO) */
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UNIPHIER_RESETX(40, 0x2008, 0), /* AIO */
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UNIPHIER_RESETX(41, 0x2008, 1), /* EVEA */
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UNIPHIER_RESETX(42, 0x2010, 2), /* EXIV */
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UNIPHIER_RESET_END,
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};
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static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
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UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
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UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
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UNIPHIER_RESETX(6, 0x200c, 6), /* Ether */
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UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC) */
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UNIPHIER_RESETX(12, 0x200c, 5), /* GIO (PCIe, USB3) */
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UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
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UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */
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UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */
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UNIPHIER_RESETX(19, 0x200c, 15), /* USB30-PHY3 */
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UNIPHIER_RESETX(40, 0x2008, 0), /* AIO */
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UNIPHIER_RESETX(41, 0x2008, 1), /* EVEA */
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UNIPHIER_RESETX(42, 0x2010, 2), /* EXIV */
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UNIPHIER_RESET_END,
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};
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static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
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UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
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UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
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UNIPHIER_RESETX(6, 0x200c, 9), /* Ether0 */
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UNIPHIER_RESETX(7, 0x200c, 10), /* Ether1 */
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UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */
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UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link (GIO0) */
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UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link (GIO1) */
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UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY0 */
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UNIPHIER_RESETX(17, 0x200c, 18), /* USB30-PHY1 */
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UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */
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UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */
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UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */
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UNIPHIER_RESET_END,
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};
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/* Media I/O reset data */
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#define UNIPHIER_MIO_RESET_SD(id, ch) \
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UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)
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#define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \
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UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26)
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#define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \
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UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0)
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#define UNIPHIER_MIO_RESET_USB2(id, ch) \
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UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0)
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#define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \
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UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24)
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#define UNIPHIER_MIO_RESET_DMAC(id) \
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UNIPHIER_RESETX((id), 0x110, 17)
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static const struct uniphier_reset_data uniphier_ld4_mio_reset_data[] = {
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UNIPHIER_MIO_RESET_SD(0, 0),
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UNIPHIER_MIO_RESET_SD(1, 1),
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UNIPHIER_MIO_RESET_SD(2, 2),
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UNIPHIER_MIO_RESET_SD_BRIDGE(3, 0),
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UNIPHIER_MIO_RESET_SD_BRIDGE(4, 1),
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UNIPHIER_MIO_RESET_SD_BRIDGE(5, 2),
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UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
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UNIPHIER_MIO_RESET_DMAC(7),
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UNIPHIER_MIO_RESET_USB2(8, 0),
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UNIPHIER_MIO_RESET_USB2(9, 1),
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UNIPHIER_MIO_RESET_USB2(10, 2),
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UNIPHIER_MIO_RESET_USB2_BRIDGE(12, 0),
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UNIPHIER_MIO_RESET_USB2_BRIDGE(13, 1),
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UNIPHIER_MIO_RESET_USB2_BRIDGE(14, 2),
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UNIPHIER_RESET_END,
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};
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static const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = {
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UNIPHIER_MIO_RESET_SD(0, 0),
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UNIPHIER_MIO_RESET_SD(1, 1),
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UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
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UNIPHIER_RESET_END,
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};
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/* Peripheral reset data */
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#define UNIPHIER_PERI_RESET_UART(id, ch) \
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UNIPHIER_RESETX((id), 0x114, 19 + (ch))
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#define UNIPHIER_PERI_RESET_I2C(id, ch) \
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UNIPHIER_RESETX((id), 0x114, 5 + (ch))
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#define UNIPHIER_PERI_RESET_FI2C(id, ch) \
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UNIPHIER_RESETX((id), 0x114, 24 + (ch))
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static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
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UNIPHIER_PERI_RESET_UART(0, 0),
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UNIPHIER_PERI_RESET_UART(1, 1),
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UNIPHIER_PERI_RESET_UART(2, 2),
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UNIPHIER_PERI_RESET_UART(3, 3),
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UNIPHIER_PERI_RESET_I2C(4, 0),
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UNIPHIER_PERI_RESET_I2C(5, 1),
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UNIPHIER_PERI_RESET_I2C(6, 2),
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UNIPHIER_PERI_RESET_I2C(7, 3),
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UNIPHIER_PERI_RESET_I2C(8, 4),
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UNIPHIER_RESET_END,
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};
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static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
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UNIPHIER_PERI_RESET_UART(0, 0),
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UNIPHIER_PERI_RESET_UART(1, 1),
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UNIPHIER_PERI_RESET_UART(2, 2),
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UNIPHIER_PERI_RESET_UART(3, 3),
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UNIPHIER_PERI_RESET_FI2C(4, 0),
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UNIPHIER_PERI_RESET_FI2C(5, 1),
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UNIPHIER_PERI_RESET_FI2C(6, 2),
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UNIPHIER_PERI_RESET_FI2C(7, 3),
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UNIPHIER_PERI_RESET_FI2C(8, 4),
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UNIPHIER_PERI_RESET_FI2C(9, 5),
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UNIPHIER_PERI_RESET_FI2C(10, 6),
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UNIPHIER_RESET_END,
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};
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/* Analog signal amplifiers reset data */
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static const struct uniphier_reset_data uniphier_ld11_adamv_reset_data[] = {
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UNIPHIER_RESETX(0, 0x10, 6), /* EVEA */
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UNIPHIER_RESET_END,
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};
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/* core implementaton */
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struct uniphier_reset_priv {
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struct reset_controller_dev rcdev;
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struct device *dev;
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struct regmap *regmap;
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const struct uniphier_reset_data *data;
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};
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#define to_uniphier_reset_priv(_rcdev) \
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container_of(_rcdev, struct uniphier_reset_priv, rcdev)
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static int uniphier_reset_update(struct reset_controller_dev *rcdev,
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unsigned long id, int assert)
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{
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struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev);
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const struct uniphier_reset_data *p;
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for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
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unsigned int mask, val;
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if (p->id != id)
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continue;
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mask = BIT(p->bit);
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if (assert)
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val = mask;
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else
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val = ~mask;
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if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
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val = ~val;
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return regmap_write_bits(priv->regmap, p->reg, mask, val);
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}
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dev_err(priv->dev, "reset_id=%lu was not handled\n", id);
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return -EINVAL;
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}
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static int uniphier_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return uniphier_reset_update(rcdev, id, 1);
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}
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static int uniphier_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return uniphier_reset_update(rcdev, id, 0);
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}
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static int uniphier_reset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev);
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const struct uniphier_reset_data *p;
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for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
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unsigned int val;
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int ret, asserted;
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if (p->id != id)
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continue;
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ret = regmap_read(priv->regmap, p->reg, &val);
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if (ret)
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return ret;
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asserted = !!(val & BIT(p->bit));
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if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
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asserted = !asserted;
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return asserted;
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}
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dev_err(priv->dev, "reset_id=%lu was not found\n", id);
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return -EINVAL;
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}
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static const struct reset_control_ops uniphier_reset_ops = {
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.assert = uniphier_reset_assert,
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.deassert = uniphier_reset_deassert,
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.status = uniphier_reset_status,
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};
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static int uniphier_reset_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct uniphier_reset_priv *priv;
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const struct uniphier_reset_data *p, *data;
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struct regmap *regmap;
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struct device_node *parent;
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unsigned int nr_resets = 0;
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data = of_device_get_match_data(dev);
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if (WARN_ON(!data))
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return -EINVAL;
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parent = of_get_parent(dev->of_node); /* parent should be syscon node */
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regmap = syscon_node_to_regmap(parent);
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of_node_put(parent);
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if (IS_ERR(regmap)) {
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dev_err(dev, "failed to get regmap (error %ld)\n",
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PTR_ERR(regmap));
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return PTR_ERR(regmap);
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}
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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for (p = data; p->id != UNIPHIER_RESET_ID_END; p++)
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nr_resets = max(nr_resets, p->id + 1);
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priv->rcdev.ops = &uniphier_reset_ops;
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priv->rcdev.owner = dev->driver->owner;
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priv->rcdev.of_node = dev->of_node;
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priv->rcdev.nr_resets = nr_resets;
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priv->dev = dev;
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priv->regmap = regmap;
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priv->data = data;
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return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
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}
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static const struct of_device_id uniphier_reset_match[] = {
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/* System reset */
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{
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.compatible = "socionext,uniphier-ld4-reset",
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.data = uniphier_ld4_sys_reset_data,
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},
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{
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.compatible = "socionext,uniphier-pro4-reset",
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.data = uniphier_pro4_sys_reset_data,
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},
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{
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.compatible = "socionext,uniphier-sld8-reset",
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.data = uniphier_ld4_sys_reset_data,
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},
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{
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.compatible = "socionext,uniphier-pro5-reset",
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.data = uniphier_pro5_sys_reset_data,
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},
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{
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.compatible = "socionext,uniphier-pxs2-reset",
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.data = uniphier_pxs2_sys_reset_data,
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},
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{
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.compatible = "socionext,uniphier-ld11-reset",
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.data = uniphier_ld11_sys_reset_data,
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},
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{
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.compatible = "socionext,uniphier-ld20-reset",
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.data = uniphier_ld20_sys_reset_data,
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},
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{
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.compatible = "socionext,uniphier-pxs3-reset",
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.data = uniphier_pxs3_sys_reset_data,
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},
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/* Media I/O reset, SD reset */
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{
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.compatible = "socionext,uniphier-ld4-mio-reset",
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.data = uniphier_ld4_mio_reset_data,
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},
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{
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.compatible = "socionext,uniphier-pro4-mio-reset",
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.data = uniphier_ld4_mio_reset_data,
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},
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{
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.compatible = "socionext,uniphier-sld8-mio-reset",
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.data = uniphier_ld4_mio_reset_data,
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},
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{
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.compatible = "socionext,uniphier-pro5-sd-reset",
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.data = uniphier_pro5_sd_reset_data,
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},
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{
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.compatible = "socionext,uniphier-pxs2-sd-reset",
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.data = uniphier_pro5_sd_reset_data,
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},
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{
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.compatible = "socionext,uniphier-ld11-mio-reset",
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.data = uniphier_ld4_mio_reset_data,
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},
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{
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.compatible = "socionext,uniphier-ld11-sd-reset",
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.data = uniphier_pro5_sd_reset_data,
|
|
},
|
|
{
|
|
.compatible = "socionext,uniphier-ld20-sd-reset",
|
|
.data = uniphier_pro5_sd_reset_data,
|
|
},
|
|
{
|
|
.compatible = "socionext,uniphier-pxs3-sd-reset",
|
|
.data = uniphier_pro5_sd_reset_data,
|
|
},
|
|
/* Peripheral reset */
|
|
{
|
|
.compatible = "socionext,uniphier-ld4-peri-reset",
|
|
.data = uniphier_ld4_peri_reset_data,
|
|
},
|
|
{
|
|
.compatible = "socionext,uniphier-pro4-peri-reset",
|
|
.data = uniphier_pro4_peri_reset_data,
|
|
},
|
|
{
|
|
.compatible = "socionext,uniphier-sld8-peri-reset",
|
|
.data = uniphier_ld4_peri_reset_data,
|
|
},
|
|
{
|
|
.compatible = "socionext,uniphier-pro5-peri-reset",
|
|
.data = uniphier_pro4_peri_reset_data,
|
|
},
|
|
{
|
|
.compatible = "socionext,uniphier-pxs2-peri-reset",
|
|
.data = uniphier_pro4_peri_reset_data,
|
|
},
|
|
{
|
|
.compatible = "socionext,uniphier-ld11-peri-reset",
|
|
.data = uniphier_pro4_peri_reset_data,
|
|
},
|
|
{
|
|
.compatible = "socionext,uniphier-ld20-peri-reset",
|
|
.data = uniphier_pro4_peri_reset_data,
|
|
},
|
|
{
|
|
.compatible = "socionext,uniphier-pxs3-peri-reset",
|
|
.data = uniphier_pro4_peri_reset_data,
|
|
},
|
|
/* Analog signal amplifiers reset */
|
|
{
|
|
.compatible = "socionext,uniphier-ld11-adamv-reset",
|
|
.data = uniphier_ld11_adamv_reset_data,
|
|
},
|
|
{
|
|
.compatible = "socionext,uniphier-ld20-adamv-reset",
|
|
.data = uniphier_ld11_adamv_reset_data,
|
|
},
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, uniphier_reset_match);
|
|
|
|
static struct platform_driver uniphier_reset_driver = {
|
|
.probe = uniphier_reset_probe,
|
|
.driver = {
|
|
.name = "uniphier-reset",
|
|
.of_match_table = uniphier_reset_match,
|
|
},
|
|
};
|
|
module_platform_driver(uniphier_reset_driver);
|
|
|
|
MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
|
|
MODULE_DESCRIPTION("UniPhier Reset Controller Driver");
|
|
MODULE_LICENSE("GPL");
|