mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
e70f466067
Signed-off-by: Steven Miao <realmz6@gmail.com> Signed-off-by: Bob Liu <lliubbo@gmail.com>
613 lines
17 KiB
C
613 lines
17 KiB
C
/*
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* bfin_dma.c - Blackfin DMA implementation
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*
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/param.h>
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#include <linux/proc_fs.h>
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#include <linux/sched.h>
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#include <linux/seq_file.h>
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#include <linux/spinlock.h>
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#include <asm/blackfin.h>
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#include <asm/cacheflush.h>
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#include <asm/dma.h>
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#include <asm/uaccess.h>
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#include <asm/early_printk.h>
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/*
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* To make sure we work around 05000119 - we always check DMA_DONE bit,
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* never the DMA_RUN bit
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*/
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struct dma_channel dma_ch[MAX_DMA_CHANNELS];
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EXPORT_SYMBOL(dma_ch);
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static int __init blackfin_dma_init(void)
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{
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int i;
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printk(KERN_INFO "Blackfin DMA Controller\n");
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#if ANOMALY_05000480
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bfin_write_DMAC_TC_PER(0x0111);
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#endif
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for (i = 0; i < MAX_DMA_CHANNELS; i++) {
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atomic_set(&dma_ch[i].chan_status, 0);
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dma_ch[i].regs = dma_io_base_addr[i];
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}
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#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
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/* Mark MEMDMA Channel 3 as requested since we're using it internally */
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request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy");
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request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy");
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#else
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/* Mark MEMDMA Channel 0 as requested since we're using it internally */
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request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
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request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy");
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#endif
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#if defined(CONFIG_DEB_DMA_URGENT)
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bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
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| DEB1_URGENT | DEB2_URGENT | DEB3_URGENT);
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#endif
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return 0;
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}
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arch_initcall(blackfin_dma_init);
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#ifdef CONFIG_PROC_FS
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static int proc_dma_show(struct seq_file *m, void *v)
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{
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int i;
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for (i = 0; i < MAX_DMA_CHANNELS; ++i)
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if (dma_channel_active(i))
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seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id);
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return 0;
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}
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static int proc_dma_open(struct inode *inode, struct file *file)
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{
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return single_open(file, proc_dma_show, NULL);
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}
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static const struct file_operations proc_dma_operations = {
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.open = proc_dma_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int __init proc_dma_init(void)
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{
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proc_create("dma", 0, NULL, &proc_dma_operations);
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return 0;
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}
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late_initcall(proc_dma_init);
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#endif
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static void set_dma_peripheral_map(unsigned int channel, const char *device_id)
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{
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#ifdef CONFIG_BF54x
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unsigned int per_map;
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switch (channel) {
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case CH_UART2_RX: per_map = 0xC << 12; break;
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case CH_UART2_TX: per_map = 0xD << 12; break;
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case CH_UART3_RX: per_map = 0xE << 12; break;
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case CH_UART3_TX: per_map = 0xF << 12; break;
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default: return;
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}
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if (strncmp(device_id, "BFIN_UART", 9) == 0)
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dma_ch[channel].regs->peripheral_map = per_map;
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#endif
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}
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/**
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* request_dma - request a DMA channel
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*
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* Request the specific DMA channel from the system if it's available.
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*/
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int request_dma(unsigned int channel, const char *device_id)
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{
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pr_debug("request_dma() : BEGIN\n");
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if (device_id == NULL)
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printk(KERN_WARNING "request_dma(%u): no device_id given\n", channel);
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#if defined(CONFIG_BF561) && ANOMALY_05000182
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if (channel >= CH_IMEM_STREAM0_DEST && channel <= CH_IMEM_STREAM1_DEST) {
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if (get_cclk() > 500000000) {
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printk(KERN_WARNING
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"Request IMDMA failed due to ANOMALY 05000182\n");
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return -EFAULT;
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}
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}
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#endif
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if (atomic_cmpxchg(&dma_ch[channel].chan_status, 0, 1)) {
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pr_debug("DMA CHANNEL IN USE\n");
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return -EBUSY;
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}
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set_dma_peripheral_map(channel, device_id);
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dma_ch[channel].device_id = device_id;
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dma_ch[channel].irq = 0;
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/* This is to be enabled by putting a restriction -
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* you have to request DMA, before doing any operations on
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* descriptor/channel
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*/
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pr_debug("request_dma() : END\n");
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return 0;
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}
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EXPORT_SYMBOL(request_dma);
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int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data)
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{
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int ret;
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unsigned int irq;
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BUG_ON(channel >= MAX_DMA_CHANNELS || !callback ||
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!atomic_read(&dma_ch[channel].chan_status));
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irq = channel2irq(channel);
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ret = request_irq(irq, callback, 0, dma_ch[channel].device_id, data);
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if (ret)
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return ret;
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dma_ch[channel].irq = irq;
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dma_ch[channel].data = data;
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return 0;
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}
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EXPORT_SYMBOL(set_dma_callback);
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/**
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* clear_dma_buffer - clear DMA fifos for specified channel
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*
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* Set the Buffer Clear bit in the Configuration register of specific DMA
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* channel. This will stop the descriptor based DMA operation.
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*/
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static void clear_dma_buffer(unsigned int channel)
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{
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dma_ch[channel].regs->cfg |= RESTART;
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SSYNC();
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dma_ch[channel].regs->cfg &= ~RESTART;
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}
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void free_dma(unsigned int channel)
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{
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pr_debug("freedma() : BEGIN\n");
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BUG_ON(channel >= MAX_DMA_CHANNELS ||
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!atomic_read(&dma_ch[channel].chan_status));
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/* Halt the DMA */
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disable_dma(channel);
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clear_dma_buffer(channel);
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if (dma_ch[channel].irq)
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free_irq(dma_ch[channel].irq, dma_ch[channel].data);
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/* Clear the DMA Variable in the Channel */
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atomic_set(&dma_ch[channel].chan_status, 0);
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pr_debug("freedma() : END\n");
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}
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EXPORT_SYMBOL(free_dma);
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#ifdef CONFIG_PM
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# ifndef MAX_DMA_SUSPEND_CHANNELS
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# define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS
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# endif
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# ifndef CONFIG_BF60x
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int blackfin_dma_suspend(void)
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{
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int i;
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for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
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if (dma_ch[i].regs->cfg & DMAEN) {
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printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
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return -EBUSY;
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}
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if (i < MAX_DMA_SUSPEND_CHANNELS)
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dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
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}
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#if ANOMALY_05000480
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bfin_write_DMAC_TC_PER(0x0);
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#endif
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return 0;
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}
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void blackfin_dma_resume(void)
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{
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int i;
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for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
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dma_ch[i].regs->cfg = 0;
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if (i < MAX_DMA_SUSPEND_CHANNELS)
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dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
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}
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#if ANOMALY_05000480
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bfin_write_DMAC_TC_PER(0x0111);
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#endif
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}
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# else
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int blackfin_dma_suspend(void)
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{
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return 0;
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}
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void blackfin_dma_resume(void)
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{
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}
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#endif
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#endif
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/**
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* blackfin_dma_early_init - minimal DMA init
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*
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* Setup a few DMA registers so we can safely do DMA transfers early on in
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* the kernel booting process. Really this just means using dma_memcpy().
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*/
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void __init blackfin_dma_early_init(void)
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{
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early_shadow_stamp();
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bfin_write_MDMA_S0_CONFIG(0);
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bfin_write_MDMA_S1_CONFIG(0);
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}
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void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
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{
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unsigned long dst = (unsigned long)pdst;
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unsigned long src = (unsigned long)psrc;
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struct dma_register *dst_ch, *src_ch;
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early_shadow_stamp();
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/* We assume that everything is 4 byte aligned, so include
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* a basic sanity check
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*/
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BUG_ON(dst % 4);
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BUG_ON(src % 4);
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BUG_ON(size % 4);
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src_ch = 0;
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/* Find an avalible memDMA channel */
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while (1) {
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if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) {
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dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR;
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src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR;
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} else {
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dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR;
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src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
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}
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if (!DMA_MMR_READ(&src_ch->cfg))
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break;
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else if (DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE) {
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DMA_MMR_WRITE(&src_ch->cfg, 0);
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break;
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}
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}
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/* Force a sync in case a previous config reset on this channel
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* occurred. This is needed so subsequent writes to DMA registers
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* are not spuriously lost/corrupted.
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*/
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__builtin_bfin_ssync();
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/* Destination */
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bfin_write32(&dst_ch->start_addr, dst);
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DMA_MMR_WRITE(&dst_ch->x_count, size >> 2);
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DMA_MMR_WRITE(&dst_ch->x_modify, 1 << 2);
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DMA_MMR_WRITE(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
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/* Source */
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bfin_write32(&src_ch->start_addr, src);
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DMA_MMR_WRITE(&src_ch->x_count, size >> 2);
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DMA_MMR_WRITE(&src_ch->x_modify, 1 << 2);
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DMA_MMR_WRITE(&src_ch->irq_status, DMA_DONE | DMA_ERR);
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/* Enable */
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DMA_MMR_WRITE(&src_ch->cfg, DMAEN | WDSIZE_32);
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DMA_MMR_WRITE(&dst_ch->cfg, WNR | DI_EN_X | DMAEN | WDSIZE_32);
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/* Since we are atomic now, don't use the workaround ssync */
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__builtin_bfin_ssync();
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#ifdef CONFIG_BF60x
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/* Work around a possible MDMA anomaly. Running 2 MDMA channels to
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* transfer DDR data to L1 SRAM may corrupt data.
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* Should be reverted after this issue is root caused.
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*/
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while (!(DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE))
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continue;
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#endif
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}
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void __init early_dma_memcpy_done(void)
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{
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early_shadow_stamp();
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while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) ||
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(bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE)))
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continue;
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bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
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bfin_write_MDMA_D1_IRQ_STATUS(DMA_DONE | DMA_ERR);
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/*
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* Now that DMA is done, we would normally flush cache, but
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* i/d cache isn't running this early, so we don't bother,
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* and just clear out the DMA channel for next time
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*/
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bfin_write_MDMA_S0_CONFIG(0);
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bfin_write_MDMA_S1_CONFIG(0);
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bfin_write_MDMA_D0_CONFIG(0);
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bfin_write_MDMA_D1_CONFIG(0);
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__builtin_bfin_ssync();
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}
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#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
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#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
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#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
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#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
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#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S3_IRQ_STATUS
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#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S3_X_COUNT
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#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S3_X_MODIFY
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#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S3_Y_COUNT
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#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S3_Y_MODIFY
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#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D3_CONFIG
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#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D3_START_ADDR
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#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D3_IRQ_STATUS
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#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D3_IRQ_STATUS
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#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D3_X_COUNT
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#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D3_X_MODIFY
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#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D3_Y_COUNT
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#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D3_Y_MODIFY
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#else
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#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S0_CONFIG
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#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S0_CONFIG
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#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S0_START_ADDR
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#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S0_IRQ_STATUS
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#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S0_X_COUNT
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#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S0_X_MODIFY
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#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S0_Y_COUNT
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#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S0_Y_MODIFY
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#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D0_CONFIG
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#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D0_START_ADDR
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#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D0_IRQ_STATUS
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#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D0_IRQ_STATUS
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#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D0_X_COUNT
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#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D0_X_MODIFY
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#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D0_Y_COUNT
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#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D0_Y_MODIFY
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#endif
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/**
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* __dma_memcpy - program the MDMA registers
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*
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* Actually program MDMA0 and wait for the transfer to finish. Disable IRQs
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* while programming registers so that everything is fully configured. Wait
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* for DMA to finish with IRQs enabled. If interrupted, the initial DMA_DONE
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* check will make sure we don't clobber any existing transfer.
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*/
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static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u32 conf)
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{
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static DEFINE_SPINLOCK(mdma_lock);
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unsigned long flags;
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spin_lock_irqsave(&mdma_lock, flags);
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/* Force a sync in case a previous config reset on this channel
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* occurred. This is needed so subsequent writes to DMA registers
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* are not spuriously lost/corrupted. Do it under irq lock and
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* without the anomaly version (because we are atomic already).
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*/
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__builtin_bfin_ssync();
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if (bfin_read_MDMA_S_CONFIG())
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while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
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continue;
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if (conf & DMA2D) {
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/* For larger bit sizes, we've already divided down cnt so it
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* is no longer a multiple of 64k. So we have to break down
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* the limit here so it is a multiple of the incoming size.
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* There is no limitation here in terms of total size other
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* than the hardware though as the bits lost in the shift are
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* made up by MODIFY (== we can hit the whole address space).
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* X: (2^(16 - 0)) * 1 == (2^(16 - 1)) * 2 == (2^(16 - 2)) * 4
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*/
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u32 shift = abs(dmod) >> 1;
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size_t ycnt = cnt >> (16 - shift);
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cnt = 1 << (16 - shift);
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bfin_write_MDMA_D_Y_COUNT(ycnt);
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bfin_write_MDMA_S_Y_COUNT(ycnt);
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bfin_write_MDMA_D_Y_MODIFY(dmod);
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bfin_write_MDMA_S_Y_MODIFY(smod);
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}
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bfin_write_MDMA_D_START_ADDR(daddr);
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bfin_write_MDMA_D_X_COUNT(cnt);
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bfin_write_MDMA_D_X_MODIFY(dmod);
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bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
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bfin_write_MDMA_S_START_ADDR(saddr);
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bfin_write_MDMA_S_X_COUNT(cnt);
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bfin_write_MDMA_S_X_MODIFY(smod);
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bfin_write_MDMA_S_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S_CONFIG(DMAEN | conf);
|
|
if (conf & DMA2D)
|
|
bfin_write_MDMA_D_CONFIG(WNR | DI_EN_Y | DMAEN | conf);
|
|
else
|
|
bfin_write_MDMA_D_CONFIG(WNR | DI_EN_X | DMAEN | conf);
|
|
|
|
spin_unlock_irqrestore(&mdma_lock, flags);
|
|
|
|
SSYNC();
|
|
|
|
while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
|
|
if (bfin_read_MDMA_S_CONFIG())
|
|
continue;
|
|
else
|
|
return;
|
|
|
|
bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S_CONFIG(0);
|
|
bfin_write_MDMA_D_CONFIG(0);
|
|
}
|
|
|
|
/**
|
|
* _dma_memcpy - translate C memcpy settings into MDMA settings
|
|
*
|
|
* Handle all the high level steps before we touch the MDMA registers. So
|
|
* handle direction, tweaking of sizes, and formatting of addresses.
|
|
*/
|
|
static void *_dma_memcpy(void *pdst, const void *psrc, size_t size)
|
|
{
|
|
u32 conf, shift;
|
|
s16 mod;
|
|
unsigned long dst = (unsigned long)pdst;
|
|
unsigned long src = (unsigned long)psrc;
|
|
|
|
if (size == 0)
|
|
return NULL;
|
|
|
|
if (dst % 4 == 0 && src % 4 == 0 && size % 4 == 0) {
|
|
conf = WDSIZE_32;
|
|
shift = 2;
|
|
} else if (dst % 2 == 0 && src % 2 == 0 && size % 2 == 0) {
|
|
conf = WDSIZE_16;
|
|
shift = 1;
|
|
} else {
|
|
conf = WDSIZE_8;
|
|
shift = 0;
|
|
}
|
|
|
|
/* If the two memory regions have a chance of overlapping, make
|
|
* sure the memcpy still works as expected. Do this by having the
|
|
* copy run backwards instead.
|
|
*/
|
|
mod = 1 << shift;
|
|
if (src < dst) {
|
|
mod *= -1;
|
|
dst += size + mod;
|
|
src += size + mod;
|
|
}
|
|
size >>= shift;
|
|
|
|
#ifndef DMA_MMR_SIZE_32
|
|
if (size > 0x10000)
|
|
conf |= DMA2D;
|
|
#endif
|
|
|
|
__dma_memcpy(dst, mod, src, mod, size, conf);
|
|
|
|
return pdst;
|
|
}
|
|
|
|
/**
|
|
* dma_memcpy - DMA memcpy under mutex lock
|
|
*
|
|
* Do not check arguments before starting the DMA memcpy. Break the transfer
|
|
* up into two pieces. The first transfer is in multiples of 64k and the
|
|
* second transfer is the piece smaller than 64k.
|
|
*/
|
|
void *dma_memcpy(void *pdst, const void *psrc, size_t size)
|
|
{
|
|
unsigned long dst = (unsigned long)pdst;
|
|
unsigned long src = (unsigned long)psrc;
|
|
|
|
if (bfin_addr_dcacheable(src))
|
|
blackfin_dcache_flush_range(src, src + size);
|
|
|
|
if (bfin_addr_dcacheable(dst))
|
|
blackfin_dcache_invalidate_range(dst, dst + size);
|
|
|
|
return dma_memcpy_nocache(pdst, psrc, size);
|
|
}
|
|
EXPORT_SYMBOL(dma_memcpy);
|
|
|
|
/**
|
|
* dma_memcpy_nocache - DMA memcpy under mutex lock
|
|
* - No cache flush/invalidate
|
|
*
|
|
* Do not check arguments before starting the DMA memcpy. Break the transfer
|
|
* up into two pieces. The first transfer is in multiples of 64k and the
|
|
* second transfer is the piece smaller than 64k.
|
|
*/
|
|
void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
|
|
{
|
|
#ifdef DMA_MMR_SIZE_32
|
|
_dma_memcpy(pdst, psrc, size);
|
|
#else
|
|
size_t bulk, rest;
|
|
|
|
bulk = size & ~0xffff;
|
|
rest = size - bulk;
|
|
if (bulk)
|
|
_dma_memcpy(pdst, psrc, bulk);
|
|
_dma_memcpy(pdst + bulk, psrc + bulk, rest);
|
|
#endif
|
|
return pdst;
|
|
}
|
|
EXPORT_SYMBOL(dma_memcpy_nocache);
|
|
|
|
/**
|
|
* safe_dma_memcpy - DMA memcpy w/argument checking
|
|
*
|
|
* Verify arguments are safe before heading to dma_memcpy().
|
|
*/
|
|
void *safe_dma_memcpy(void *dst, const void *src, size_t size)
|
|
{
|
|
if (!access_ok(VERIFY_WRITE, dst, size))
|
|
return NULL;
|
|
if (!access_ok(VERIFY_READ, src, size))
|
|
return NULL;
|
|
return dma_memcpy(dst, src, size);
|
|
}
|
|
EXPORT_SYMBOL(safe_dma_memcpy);
|
|
|
|
static void _dma_out(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
|
|
u16 size, u16 dma_size)
|
|
{
|
|
blackfin_dcache_flush_range(buf, buf + len * size);
|
|
__dma_memcpy(addr, 0, buf, size, len, dma_size);
|
|
}
|
|
|
|
static void _dma_in(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
|
|
u16 size, u16 dma_size)
|
|
{
|
|
blackfin_dcache_invalidate_range(buf, buf + len * size);
|
|
__dma_memcpy(buf, size, addr, 0, len, dma_size);
|
|
}
|
|
|
|
#define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \
|
|
void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned DMA_MMR_SIZE_TYPE len) \
|
|
{ \
|
|
_dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \
|
|
} \
|
|
EXPORT_SYMBOL(dma_##io##s##bwl)
|
|
MAKE_DMA_IO(out, b, 1, 8, const);
|
|
MAKE_DMA_IO(in, b, 1, 8, );
|
|
MAKE_DMA_IO(out, w, 2, 16, const);
|
|
MAKE_DMA_IO(in, w, 2, 16, );
|
|
MAKE_DMA_IO(out, l, 4, 32, const);
|
|
MAKE_DMA_IO(in, l, 4, 32, );
|