mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 02:56:38 +07:00
63288b721a
Let's say clock A and B are two gate clocks that share the same register
bit in hardware. Therefore they are registered as shared gate clocks
with imx_clk_gate2_shared().
In a scenario that only clock A is enabled by clk_enable(A) while B is
not used, the shared gate will be unexpectedly disabled in hardware.
It happens because clk_enable(A) increments the share_count from 0 to 1,
while clock B is unused to clock core, and therefore the core function
will just disable B by calling clk->ops->disable() directly. The
consequence of that call is share_count is decremented to 0 and the gate
is disabled in hardware, even though clock A is still in use.
The patch fixes the issue by initializing the share_count per hardware
state and returns enable state per share_count from .is_enabled() hook,
in case it's a shared gate.
While at it, add a check in clk_gate2_disable() to ensure it's never
called with a zero share_count.
Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
Fixes: f9f28cdf21 ("ARM: imx: add shared gate clock support")
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
150 lines
3.3 KiB
C
150 lines
3.3 KiB
C
/*
|
|
* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
|
|
* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* Gated clock implementation
|
|
*/
|
|
|
|
#include <linux/clk-provider.h>
|
|
#include <linux/module.h>
|
|
#include <linux/slab.h>
|
|
#include <linux/io.h>
|
|
#include <linux/err.h>
|
|
#include <linux/string.h>
|
|
#include "clk.h"
|
|
|
|
/**
|
|
* DOC: basic gatable clock which can gate and ungate it's ouput
|
|
*
|
|
* Traits of this clock:
|
|
* prepare - clk_(un)prepare only ensures parent is (un)prepared
|
|
* enable - clk_enable and clk_disable are functional & control gating
|
|
* rate - inherits rate from parent. No clk_set_rate support
|
|
* parent - fixed parent. No clk_set_parent support
|
|
*/
|
|
|
|
struct clk_gate2 {
|
|
struct clk_hw hw;
|
|
void __iomem *reg;
|
|
u8 bit_idx;
|
|
u8 flags;
|
|
spinlock_t *lock;
|
|
unsigned int *share_count;
|
|
};
|
|
|
|
#define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw)
|
|
|
|
static int clk_gate2_enable(struct clk_hw *hw)
|
|
{
|
|
struct clk_gate2 *gate = to_clk_gate2(hw);
|
|
u32 reg;
|
|
unsigned long flags = 0;
|
|
|
|
spin_lock_irqsave(gate->lock, flags);
|
|
|
|
if (gate->share_count && (*gate->share_count)++ > 0)
|
|
goto out;
|
|
|
|
reg = readl(gate->reg);
|
|
reg |= 3 << gate->bit_idx;
|
|
writel(reg, gate->reg);
|
|
|
|
out:
|
|
spin_unlock_irqrestore(gate->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void clk_gate2_disable(struct clk_hw *hw)
|
|
{
|
|
struct clk_gate2 *gate = to_clk_gate2(hw);
|
|
u32 reg;
|
|
unsigned long flags = 0;
|
|
|
|
spin_lock_irqsave(gate->lock, flags);
|
|
|
|
if (gate->share_count) {
|
|
if (WARN_ON(*gate->share_count == 0))
|
|
goto out;
|
|
else if (--(*gate->share_count) > 0)
|
|
goto out;
|
|
}
|
|
|
|
reg = readl(gate->reg);
|
|
reg &= ~(3 << gate->bit_idx);
|
|
writel(reg, gate->reg);
|
|
|
|
out:
|
|
spin_unlock_irqrestore(gate->lock, flags);
|
|
}
|
|
|
|
static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx)
|
|
{
|
|
u32 val = readl(reg);
|
|
|
|
if (((val >> bit_idx) & 1) == 1)
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int clk_gate2_is_enabled(struct clk_hw *hw)
|
|
{
|
|
struct clk_gate2 *gate = to_clk_gate2(hw);
|
|
|
|
if (gate->share_count)
|
|
return !!(*gate->share_count);
|
|
else
|
|
return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
|
|
}
|
|
|
|
static struct clk_ops clk_gate2_ops = {
|
|
.enable = clk_gate2_enable,
|
|
.disable = clk_gate2_disable,
|
|
.is_enabled = clk_gate2_is_enabled,
|
|
};
|
|
|
|
struct clk *clk_register_gate2(struct device *dev, const char *name,
|
|
const char *parent_name, unsigned long flags,
|
|
void __iomem *reg, u8 bit_idx,
|
|
u8 clk_gate2_flags, spinlock_t *lock,
|
|
unsigned int *share_count)
|
|
{
|
|
struct clk_gate2 *gate;
|
|
struct clk *clk;
|
|
struct clk_init_data init;
|
|
|
|
gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL);
|
|
if (!gate)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
/* struct clk_gate2 assignments */
|
|
gate->reg = reg;
|
|
gate->bit_idx = bit_idx;
|
|
gate->flags = clk_gate2_flags;
|
|
gate->lock = lock;
|
|
|
|
/* Initialize share_count per hardware state */
|
|
if (share_count)
|
|
*share_count = clk_gate2_reg_is_enabled(reg, bit_idx) ? 1 : 0;
|
|
gate->share_count = share_count;
|
|
|
|
init.name = name;
|
|
init.ops = &clk_gate2_ops;
|
|
init.flags = flags;
|
|
init.parent_names = parent_name ? &parent_name : NULL;
|
|
init.num_parents = parent_name ? 1 : 0;
|
|
|
|
gate->hw.init = &init;
|
|
|
|
clk = clk_register(dev, &gate->hw);
|
|
if (IS_ERR(clk))
|
|
kfree(gate);
|
|
|
|
return clk;
|
|
}
|