mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 13:33:24 +07:00
e452b818db
Make the sor1 and sor1_src clocks available on Tegra210. They will be used by the display driver to support HDMI and DP. Signed-off-by: Thierry Reding <treding@nvidia.com>
402 lines
9.4 KiB
C
402 lines
9.4 KiB
C
/*
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* This header provides constants for binding nvidia,tegra210-car.
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*
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* The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
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* registers. These IDs often match those in the CAR's RST_DEVICES registers,
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* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
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* this case, those clocks are assigned IDs above 224 in order to highlight
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* this issue. Implementations that interpret these clock IDs as bit values
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* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
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* explicitly handle these special cases.
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*
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* The balance of the clocks controlled by the CAR are assigned IDs of 224 and
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* above.
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*/
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#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
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#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
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/* 0 */
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/* 1 */
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/* 2 */
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#define TEGRA210_CLK_ISPB 3
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#define TEGRA210_CLK_RTC 4
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#define TEGRA210_CLK_TIMER 5
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#define TEGRA210_CLK_UARTA 6
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/* 7 (register bit affects uartb and vfir) */
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#define TEGRA210_CLK_GPIO 8
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#define TEGRA210_CLK_SDMMC2 9
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/* 10 (register bit affects spdif_in and spdif_out) */
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#define TEGRA210_CLK_I2S1 11
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#define TEGRA210_CLK_I2C1 12
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/* 13 */
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#define TEGRA210_CLK_SDMMC1 14
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#define TEGRA210_CLK_SDMMC4 15
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/* 16 */
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#define TEGRA210_CLK_PWM 17
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#define TEGRA210_CLK_I2S2 18
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/* 19 */
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/* 20 (register bit affects vi and vi_sensor) */
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/* 21 */
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#define TEGRA210_CLK_USBD 22
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#define TEGRA210_CLK_ISP 23
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/* 24 */
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/* 25 */
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#define TEGRA210_CLK_DISP2 26
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#define TEGRA210_CLK_DISP1 27
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#define TEGRA210_CLK_HOST1X 28
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/* 29 */
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#define TEGRA210_CLK_I2S0 30
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/* 31 */
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#define TEGRA210_CLK_MC 32
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#define TEGRA210_CLK_AHBDMA 33
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#define TEGRA210_CLK_APBDMA 34
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/* 35 */
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/* 36 */
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/* 37 */
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#define TEGRA210_CLK_PMC 38
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/* 39 (register bit affects fuse and fuse_burn) */
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#define TEGRA210_CLK_KFUSE 40
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#define TEGRA210_CLK_SBC1 41
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/* 42 */
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/* 43 */
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#define TEGRA210_CLK_SBC2 44
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/* 45 */
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#define TEGRA210_CLK_SBC3 46
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#define TEGRA210_CLK_I2C5 47
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#define TEGRA210_CLK_DSIA 48
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/* 49 */
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/* 50 */
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/* 51 */
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#define TEGRA210_CLK_CSI 52
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/* 53 */
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#define TEGRA210_CLK_I2C2 54
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#define TEGRA210_CLK_UARTC 55
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#define TEGRA210_CLK_MIPI_CAL 56
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#define TEGRA210_CLK_EMC 57
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#define TEGRA210_CLK_USB2 58
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/* 59 */
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/* 60 */
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/* 61 */
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/* 62 */
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#define TEGRA210_CLK_BSEV 63
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/* 64 */
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#define TEGRA210_CLK_UARTD 65
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/* 66 */
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#define TEGRA210_CLK_I2C3 67
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#define TEGRA210_CLK_SBC4 68
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#define TEGRA210_CLK_SDMMC3 69
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#define TEGRA210_CLK_PCIE 70
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#define TEGRA210_CLK_OWR 71
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#define TEGRA210_CLK_AFI 72
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#define TEGRA210_CLK_CSITE 73
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/* 74 */
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/* 75 */
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/* 76 */
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/* 77 */
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#define TEGRA210_CLK_SOC_THERM 78
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#define TEGRA210_CLK_DTV 79
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/* 80 */
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#define TEGRA210_CLK_I2CSLOW 81
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#define TEGRA210_CLK_DSIB 82
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#define TEGRA210_CLK_TSEC 83
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/* 84 */
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/* 85 */
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/* 86 */
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/* 87 */
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/* 88 */
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#define TEGRA210_CLK_XUSB_HOST 89
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/* 90 */
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/* 91 */
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#define TEGRA210_CLK_CSUS 92
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/* 93 */
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/* 94 */
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/* 95 (bit affects xusb_dev and xusb_dev_src) */
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/* 96 */
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/* 97 */
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/* 98 */
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#define TEGRA210_CLK_MSELECT 99
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#define TEGRA210_CLK_TSENSOR 100
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#define TEGRA210_CLK_I2S3 101
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#define TEGRA210_CLK_I2S4 102
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#define TEGRA210_CLK_I2C4 103
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/* 104 */
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/* 105 */
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#define TEGRA210_CLK_D_AUDIO 106
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#define TEGRA210_CLK_APB2APE 107
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/* 108 */
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/* 109 */
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/* 110 */
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#define TEGRA210_CLK_HDA2CODEC_2X 111
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/* 112 */
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/* 113 */
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/* 114 */
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/* 115 */
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/* 116 */
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/* 117 */
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#define TEGRA210_CLK_SPDIF_2X 118
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#define TEGRA210_CLK_ACTMON 119
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#define TEGRA210_CLK_EXTERN1 120
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#define TEGRA210_CLK_EXTERN2 121
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#define TEGRA210_CLK_EXTERN3 122
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#define TEGRA210_CLK_SATA_OOB 123
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#define TEGRA210_CLK_SATA 124
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#define TEGRA210_CLK_HDA 125
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/* 126 */
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/* 127 */
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#define TEGRA210_CLK_HDA2HDMI 128
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/* 129 */
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/* 130 */
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/* 131 */
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/* 132 */
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/* 133 */
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/* 134 */
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/* 135 */
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/* 136 */
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/* 137 */
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/* 138 */
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/* 139 */
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/* 140 */
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/* 141 */
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/* 142 */
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/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */
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#define TEGRA210_CLK_XUSB_GATE 143
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#define TEGRA210_CLK_CILAB 144
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#define TEGRA210_CLK_CILCD 145
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#define TEGRA210_CLK_CILE 146
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#define TEGRA210_CLK_DSIALP 147
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#define TEGRA210_CLK_DSIBLP 148
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#define TEGRA210_CLK_ENTROPY 149
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/* 150 */
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/* 151 */
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/* 152 */
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/* 153 */
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/* 154 */
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/* 155 (bit affects dfll_ref and dfll_soc) */
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#define TEGRA210_CLK_XUSB_SS 156
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/* 157 */
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/* 158 */
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/* 159 */
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/* 160 */
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#define TEGRA210_CLK_DMIC1 161
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#define TEGRA210_CLK_DMIC2 162
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/* 163 */
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/* 164 */
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/* 165 */
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#define TEGRA210_CLK_I2C6 166
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/* 167 */
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/* 168 */
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/* 169 */
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/* 170 */
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#define TEGRA210_CLK_VIM2_CLK 171
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/* 172 */
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#define TEGRA210_CLK_MIPIBIF 173
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/* 174 */
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/* 175 */
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/* 176 */
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#define TEGRA210_CLK_CLK72MHZ 177
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#define TEGRA210_CLK_VIC03 178
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/* 179 */
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/* 180 */
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#define TEGRA210_CLK_DPAUX 181
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#define TEGRA210_CLK_SOR0 182
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#define TEGRA210_CLK_SOR1 183
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#define TEGRA210_CLK_GPU 184
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#define TEGRA210_CLK_DBGAPB 185
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/* 186 */
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#define TEGRA210_CLK_PLL_P_OUT_ADSP 187
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/* 188 */
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#define TEGRA210_CLK_PLL_G_REF 189
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/* 190 */
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/* 191 */
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/* 192 */
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#define TEGRA210_CLK_SDMMC_LEGACY 193
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#define TEGRA210_CLK_NVDEC 194
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#define TEGRA210_CLK_NVJPG 195
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/* 196 */
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#define TEGRA210_CLK_DMIC3 197
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#define TEGRA210_CLK_APE 198
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/* 199 */
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/* 200 */
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/* 201 */
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#define TEGRA210_CLK_MAUD 202
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/* 203 */
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/* 204 */
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/* 205 */
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#define TEGRA210_CLK_TSECB 206
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#define TEGRA210_CLK_DPAUX1 207
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#define TEGRA210_CLK_VI_I2C 208
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#define TEGRA210_CLK_HSIC_TRK 209
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#define TEGRA210_CLK_USB2_TRK 210
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#define TEGRA210_CLK_QSPI 211
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#define TEGRA210_CLK_UARTAPE 212
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/* 213 */
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/* 214 */
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/* 215 */
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/* 216 */
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/* 217 */
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/* 218 */
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#define TEGRA210_CLK_NVENC 219
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/* 220 */
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/* 221 */
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#define TEGRA210_CLK_SOR_SAFE 222
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#define TEGRA210_CLK_PLL_P_OUT_CPU 223
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#define TEGRA210_CLK_UARTB 224
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#define TEGRA210_CLK_VFIR 225
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#define TEGRA210_CLK_SPDIF_IN 226
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#define TEGRA210_CLK_SPDIF_OUT 227
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#define TEGRA210_CLK_VI 228
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#define TEGRA210_CLK_VI_SENSOR 229
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#define TEGRA210_CLK_FUSE 230
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#define TEGRA210_CLK_FUSE_BURN 231
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#define TEGRA210_CLK_CLK_32K 232
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#define TEGRA210_CLK_CLK_M 233
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#define TEGRA210_CLK_CLK_M_DIV2 234
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#define TEGRA210_CLK_CLK_M_DIV4 235
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#define TEGRA210_CLK_PLL_REF 236
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#define TEGRA210_CLK_PLL_C 237
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#define TEGRA210_CLK_PLL_C_OUT1 238
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#define TEGRA210_CLK_PLL_C2 239
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#define TEGRA210_CLK_PLL_C3 240
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#define TEGRA210_CLK_PLL_M 241
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#define TEGRA210_CLK_PLL_M_OUT1 242
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#define TEGRA210_CLK_PLL_P 243
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#define TEGRA210_CLK_PLL_P_OUT1 244
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#define TEGRA210_CLK_PLL_P_OUT2 245
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#define TEGRA210_CLK_PLL_P_OUT3 246
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#define TEGRA210_CLK_PLL_P_OUT4 247
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#define TEGRA210_CLK_PLL_A 248
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#define TEGRA210_CLK_PLL_A_OUT0 249
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#define TEGRA210_CLK_PLL_D 250
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#define TEGRA210_CLK_PLL_D_OUT0 251
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#define TEGRA210_CLK_PLL_D2 252
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#define TEGRA210_CLK_PLL_D2_OUT0 253
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#define TEGRA210_CLK_PLL_U 254
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#define TEGRA210_CLK_PLL_U_480M 255
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#define TEGRA210_CLK_PLL_U_60M 256
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#define TEGRA210_CLK_PLL_U_48M 257
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/* 258 */
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#define TEGRA210_CLK_PLL_X 259
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#define TEGRA210_CLK_PLL_X_OUT0 260
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#define TEGRA210_CLK_PLL_RE_VCO 261
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#define TEGRA210_CLK_PLL_RE_OUT 262
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#define TEGRA210_CLK_PLL_E 263
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#define TEGRA210_CLK_SPDIF_IN_SYNC 264
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#define TEGRA210_CLK_I2S0_SYNC 265
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#define TEGRA210_CLK_I2S1_SYNC 266
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#define TEGRA210_CLK_I2S2_SYNC 267
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#define TEGRA210_CLK_I2S3_SYNC 268
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#define TEGRA210_CLK_I2S4_SYNC 269
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#define TEGRA210_CLK_VIMCLK_SYNC 270
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#define TEGRA210_CLK_AUDIO0 271
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#define TEGRA210_CLK_AUDIO1 272
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#define TEGRA210_CLK_AUDIO2 273
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#define TEGRA210_CLK_AUDIO3 274
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#define TEGRA210_CLK_AUDIO4 275
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#define TEGRA210_CLK_SPDIF 276
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#define TEGRA210_CLK_CLK_OUT_1 277
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#define TEGRA210_CLK_CLK_OUT_2 278
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#define TEGRA210_CLK_CLK_OUT_3 279
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#define TEGRA210_CLK_BLINK 280
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/* 281 */
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#define TEGRA210_CLK_SOR1_SRC 282
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/* 283 */
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#define TEGRA210_CLK_XUSB_HOST_SRC 284
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#define TEGRA210_CLK_XUSB_FALCON_SRC 285
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#define TEGRA210_CLK_XUSB_FS_SRC 286
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#define TEGRA210_CLK_XUSB_SS_SRC 287
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#define TEGRA210_CLK_XUSB_DEV_SRC 288
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#define TEGRA210_CLK_XUSB_DEV 289
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#define TEGRA210_CLK_XUSB_HS_SRC 290
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#define TEGRA210_CLK_SCLK 291
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#define TEGRA210_CLK_HCLK 292
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#define TEGRA210_CLK_PCLK 293
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#define TEGRA210_CLK_CCLK_G 294
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#define TEGRA210_CLK_CCLK_LP 295
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#define TEGRA210_CLK_DFLL_REF 296
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#define TEGRA210_CLK_DFLL_SOC 297
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#define TEGRA210_CLK_VI_SENSOR2 298
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#define TEGRA210_CLK_PLL_P_OUT5 299
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#define TEGRA210_CLK_CML0 300
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#define TEGRA210_CLK_CML1 301
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#define TEGRA210_CLK_PLL_C4 302
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#define TEGRA210_CLK_PLL_DP 303
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#define TEGRA210_CLK_PLL_E_MUX 304
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#define TEGRA210_CLK_PLL_MB 305
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#define TEGRA210_CLK_PLL_A1 306
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#define TEGRA210_CLK_PLL_D_DSI_OUT 307
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#define TEGRA210_CLK_PLL_C4_OUT0 308
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#define TEGRA210_CLK_PLL_C4_OUT1 309
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#define TEGRA210_CLK_PLL_C4_OUT2 310
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#define TEGRA210_CLK_PLL_C4_OUT3 311
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#define TEGRA210_CLK_PLL_U_OUT 312
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#define TEGRA210_CLK_PLL_U_OUT1 313
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#define TEGRA210_CLK_PLL_U_OUT2 314
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#define TEGRA210_CLK_USB2_HSIC_TRK 315
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#define TEGRA210_CLK_PLL_P_OUT_HSIO 316
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#define TEGRA210_CLK_PLL_P_OUT_XUSB 317
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#define TEGRA210_CLK_XUSB_SSP_SRC 318
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#define TEGRA210_CLK_PLL_RE_OUT1 319
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/* 320 */
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/* 321 */
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/* 322 */
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/* 323 */
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/* 324 */
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/* 325 */
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/* 326 */
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/* 327 */
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/* 328 */
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/* 329 */
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/* 330 */
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/* 331 */
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/* 332 */
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/* 333 */
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/* 334 */
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/* 335 */
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/* 336 */
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/* 337 */
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/* 338 */
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/* 339 */
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/* 340 */
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/* 341 */
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/* 342 */
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/* 343 */
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/* 344 */
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/* 345 */
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/* 346 */
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/* 347 */
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/* 348 */
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/* 349 */
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#define TEGRA210_CLK_AUDIO0_MUX 350
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#define TEGRA210_CLK_AUDIO1_MUX 351
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#define TEGRA210_CLK_AUDIO2_MUX 352
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#define TEGRA210_CLK_AUDIO3_MUX 353
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#define TEGRA210_CLK_AUDIO4_MUX 354
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#define TEGRA210_CLK_SPDIF_MUX 355
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#define TEGRA210_CLK_CLK_OUT_1_MUX 356
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#define TEGRA210_CLK_CLK_OUT_2_MUX 357
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#define TEGRA210_CLK_CLK_OUT_3_MUX 358
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#define TEGRA210_CLK_DSIA_MUX 359
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#define TEGRA210_CLK_DSIB_MUX 360
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#define TEGRA210_CLK_SOR0_LVDS 361
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#define TEGRA210_CLK_XUSB_SS_DIV2 362
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#define TEGRA210_CLK_PLL_M_UD 363
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#define TEGRA210_CLK_PLL_C_UD 364
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#define TEGRA210_CLK_SCLK_MUX 365
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#define TEGRA210_CLK_CLK_MAX 366
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#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
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