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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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96d4f267e4
Nobody has actually used the type (VERIFY_READ vs VERIFY_WRITE) argument
of the user address range verification function since we got rid of the
old racy i386-only code to walk page tables by hand.
It existed because the original 80386 would not honor the write protect
bit when in kernel mode, so you had to do COW by hand before doing any
user access. But we haven't supported that in a long time, and these
days the 'type' argument is a purely historical artifact.
A discussion about extending 'user_access_begin()' to do the range
checking resulted this patch, because there is no way we're going to
move the old VERIFY_xyz interface to that model. And it's best done at
the end of the merge window when I've done most of my merges, so let's
just get this done once and for all.
This patch was mostly done with a sed-script, with manual fix-ups for
the cases that weren't of the trivial 'access_ok(VERIFY_xyz' form.
There were a couple of notable cases:
- csky still had the old "verify_area()" name as an alias.
- the iter_iov code had magical hardcoded knowledge of the actual
values of VERIFY_{READ,WRITE} (not that they mattered, since nothing
really used it)
- microblaze used the type argument for a debug printout
but other than those oddities this should be a total no-op patch.
I tried to fix up all architectures, did fairly extensive grepping for
access_ok() uses, and the changes are trivial, but I may have missed
something. Any missed conversion should be trivially fixable, though.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
111 lines
2.5 KiB
C
111 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_FUTEX_H
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#define _ASM_FUTEX_H
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <asm/errno.h>
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#define __futex_atomic_op1(insn, ret, oldval, uaddr, oparg) \
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do { \
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register unsigned long r8 __asm ("r8") = 0; \
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__asm__ __volatile__( \
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" mf;; \n" \
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"[1:] " insn ";; \n" \
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" .xdata4 \"__ex_table\", 1b-., 2f-. \n" \
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"[2:]" \
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: "+r" (r8), "=r" (oldval) \
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: "r" (uaddr), "r" (oparg) \
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: "memory"); \
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ret = r8; \
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} while (0)
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#define __futex_atomic_op2(insn, ret, oldval, uaddr, oparg) \
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do { \
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register unsigned long r8 __asm ("r8") = 0; \
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int val, newval; \
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do { \
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__asm__ __volatile__( \
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" mf;; \n" \
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"[1:] ld4 %3=[%4];; \n" \
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" mov %2=%3 \n" \
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insn ";; \n" \
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" mov ar.ccv=%2;; \n" \
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"[2:] cmpxchg4.acq %1=[%4],%3,ar.ccv;; \n" \
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" .xdata4 \"__ex_table\", 1b-., 3f-.\n" \
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" .xdata4 \"__ex_table\", 2b-., 3f-.\n" \
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"[3:]" \
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: "+r" (r8), "=r" (val), "=&r" (oldval), \
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"=&r" (newval) \
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: "r" (uaddr), "r" (oparg) \
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: "memory"); \
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if (unlikely (r8)) \
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break; \
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} while (unlikely (val != oldval)); \
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ret = r8; \
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} while (0)
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static inline int
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arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
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{
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int oldval = 0, ret;
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pagefault_disable();
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op1("xchg4 %1=[%2],%3", ret, oldval, uaddr,
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oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op2("add %3=%3,%5", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op2("or %3=%3,%5", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op2("and %3=%3,%5", ret, oldval, uaddr,
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~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op2("xor %3=%3,%5", ret, oldval, uaddr, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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pagefault_enable();
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if (!ret)
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*oval = oldval;
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return ret;
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}
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static inline int
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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u32 oldval, u32 newval)
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{
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if (!access_ok(uaddr, sizeof(u32)))
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return -EFAULT;
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{
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register unsigned long r8 __asm ("r8") = 0;
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unsigned long prev;
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__asm__ __volatile__(
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" mf;; \n"
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" mov ar.ccv=%4;; \n"
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"[1:] cmpxchg4.acq %1=[%2],%3,ar.ccv \n"
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" .xdata4 \"__ex_table\", 1b-., 2f-. \n"
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"[2:]"
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: "+r" (r8), "=&r" (prev)
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: "r" (uaddr), "r" (newval),
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"rO" ((long) (unsigned) oldval)
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: "memory");
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*uval = prev;
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return r8;
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}
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}
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#endif /* _ASM_FUTEX_H */
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