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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e7b52ffd45
x86 has no flush_tlb_range support in instruction level. Currently the flush_tlb_range just implemented by flushing all page table. That is not the best solution for all scenarios. In fact, if we just use 'invlpg' to flush few lines from TLB, we can get the performance gain from later remain TLB lines accessing. But the 'invlpg' instruction costs much of time. Its execution time can compete with cr3 rewriting, and even a bit more on SNB CPU. So, on a 512 4KB TLB entries CPU, the balance points is at: (512 - X) * 100ns(assumed TLB refill cost) = X(TLB flush entries) * 100ns(assumed invlpg cost) Here, X is 256, that is 1/2 of 512 entries. But with the mysterious CPU pre-fetcher and page miss handler Unit, the assumed TLB refill cost is far lower then 100ns in sequential access. And 2 HT siblings in one core makes the memory access more faster if they are accessing the same memory. So, in the patch, I just do the change when the target entries is less than 1/16 of whole active tlb entries. Actually, I have no data support for the percentage '1/16', so any suggestions are welcomed. As to hugetlb, guess due to smaller page table, and smaller active TLB entries, I didn't see benefit via my benchmark, so no optimizing now. My micro benchmark show in ideal scenarios, the performance improves 70 percent in reading. And in worst scenario, the reading/writing performance is similar with unpatched 3.4-rc4 kernel. Here is the reading data on my 2P * 4cores *HT NHM EP machine, with THP 'always': multi thread testing, '-t' paramter is thread number: with patch unpatched 3.4-rc4 ./mprotect -t 1 14ns 24ns ./mprotect -t 2 13ns 22ns ./mprotect -t 4 12ns 19ns ./mprotect -t 8 14ns 16ns ./mprotect -t 16 28ns 26ns ./mprotect -t 32 54ns 51ns ./mprotect -t 128 200ns 199ns Single process with sequencial flushing and memory accessing: with patch unpatched 3.4-rc4 ./mprotect 7ns 11ns ./mprotect -p 4096 -l 8 -n 10240 21ns 21ns [ hpa: http://lkml.kernel.org/r/1B4B44D9196EFF41AE41FDA404FC0A100BFF94@SHSMSX101.ccr.corp.intel.com has additional performance numbers. ] Signed-off-by: Alex Shi <alex.shi@intel.com> Link: http://lkml.kernel.org/r/1340845344-27557-3-git-send-email-alex.shi@intel.com Signed-off-by: H. Peter Anvin <hpa@zytor.com>
36 lines
1.0 KiB
C
36 lines
1.0 KiB
C
#ifndef _ASM_X86_UV_UV_H
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#define _ASM_X86_UV_UV_H
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enum uv_system_type {UV_NONE, UV_LEGACY_APIC, UV_X2APIC, UV_NON_UNIQUE_APIC};
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struct cpumask;
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struct mm_struct;
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#ifdef CONFIG_X86_UV
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extern enum uv_system_type get_uv_system_type(void);
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extern int is_uv_system(void);
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extern void uv_cpu_init(void);
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extern void uv_nmi_init(void);
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extern void uv_system_init(void);
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extern const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
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struct mm_struct *mm,
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unsigned long start,
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unsigned end,
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unsigned int cpu);
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#else /* X86_UV */
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static inline enum uv_system_type get_uv_system_type(void) { return UV_NONE; }
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static inline int is_uv_system(void) { return 0; }
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static inline void uv_cpu_init(void) { }
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static inline void uv_system_init(void) { }
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static inline const struct cpumask *
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uv_flush_tlb_others(const struct cpumask *cpumask, struct mm_struct *mm,
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unsigned long start, unsigned long end, unsigned int cpu)
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{ return cpumask; }
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#endif /* X86_UV */
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#endif /* _ASM_X86_UV_UV_H */
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