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b3cd802137
Trying to access the OTP memory on the AR9340 causes a data bus error like this: Data bus error, epc == 86e84164, ra == 86e84164 Oops[#1]: Cpu 0 $ 0 : 00000000 00000061 deadc0de 00000000 $ 4 : b8115f18 00015f18 00000007 00000004 $ 8 : 00000001 7c7c3c7c 7c7c7c7c 7c7c7c7c $12 : 7c7c3c7c 001f0041 00000000 7c7c7c3c $16 : 86ee0000 00015f18 00000000 00000007 $20 : 00000004 00000064 00000004 86d71c44 $24 : 00000000 86e6ca00 $28 : 86d70000 86d71b20 86ece0c0 86e84164 Hi : 00000000 Lo : 00000064 epc : 86e84164 ath9k_hw_wait+0x58/0xb0 [ath9k_hw] Tainted: G O ra : 86e84164 ath9k_hw_wait+0x58/0xb0 [ath9k_hw] Status: 1100d403 KERNEL EXL IE Cause : 4080801c PrId : 0001974c (MIPS 74Kc) Modules linked in: ath9k(O+) ath9k_common(O) ath9k_hw(O) ath(O) ar934x_nfc mac80211(O) usbcore usb_common scsi_mod nls_base nand nand_ecc nand_ids crc_ccitt cfg80211(O) compat(O) arc4 aes_generic crypto_blkcipher cryptomgr aead crypto_hash crypto_algapi ledtrig_timer ledtrig_default_on leds_gpio Process insmod (pid: 459, threadinfo=86d70000, task=87942140, tls=779ac440) Stack : 802fb500 000200da 804db150 804e0000 87816130 86ee0000 00010000 86d71b88 86d71bc0 00000004 00000003 86e9fcd0 80305300 0002c0d0 86e74c50 800b4c20 000003e8 00000001 00000000 86ee0000 000003ff 86e9fd64 80305300 80123938 fffffffc 00000004 000058bc 00000000 86ea0000 86ee0000 000001ff 878d6000 99999999 86e9fdc0 86ee0fcc 86e9e664 0000c0d0 86ee0000 0000700000007000 ... Call Trace: [<86e84164>] ath9k_hw_wait+0x58/0xb0 [ath9k_hw] [<86e9fcd0>] ath9k_hw_setup_statusring+0x16b8/0x1c7c [ath9k_hw] Code: 0000a812 0040f809 00000000 <00531024> 1054000b 24020001 0c05b5dc 2404000a 26520001 The cause of the error is that the OTP register offsets are different on the AR9340 than the actually used values. Cc: <stable@vger.kernel.org> # 3.0+ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
343 lines
9.7 KiB
C
343 lines
9.7 KiB
C
/*
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* Copyright (c) 2010-2011 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef AR9003_EEPROM_H
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#define AR9003_EEPROM_H
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#include <linux/types.h>
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#define AR9300_EEP_VER 0xD000
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#define AR9300_EEP_VER_MINOR_MASK 0xFFF
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#define AR9300_EEP_MINOR_VER_1 0x1
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#define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
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/* 16-bit offset location start of calibration struct */
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#define AR9300_EEP_START_LOC 256
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#define AR9300_NUM_5G_CAL_PIERS 8
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#define AR9300_NUM_2G_CAL_PIERS 3
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#define AR9300_NUM_5G_20_TARGET_POWERS 8
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#define AR9300_NUM_5G_40_TARGET_POWERS 8
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#define AR9300_NUM_2G_CCK_TARGET_POWERS 2
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#define AR9300_NUM_2G_20_TARGET_POWERS 3
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#define AR9300_NUM_2G_40_TARGET_POWERS 3
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/* #define AR9300_NUM_CTLS 21 */
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#define AR9300_NUM_CTLS_5G 9
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#define AR9300_NUM_CTLS_2G 12
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#define AR9300_NUM_BAND_EDGES_5G 8
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#define AR9300_NUM_BAND_EDGES_2G 4
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#define AR9300_EEPMISC_BIG_ENDIAN 0x01
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#define AR9300_EEPMISC_WOW 0x02
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#define AR9300_CUSTOMER_DATA_SIZE 20
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#define AR9300_MAX_CHAINS 3
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#define AR9300_ANT_16S 25
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#define AR9300_FUTURE_MODAL_SZ 6
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#define AR9300_PAPRD_RATE_MASK 0x01ffffff
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#define AR9300_PAPRD_SCALE_1 0x0e000000
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#define AR9300_PAPRD_SCALE_1_S 25
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#define AR9300_PAPRD_SCALE_2 0x70000000
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#define AR9300_PAPRD_SCALE_2_S 28
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/* Delta from which to start power to pdadc table */
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/* This offset is used in both open loop and closed loop power control
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* schemes. In open loop power control, it is not really needed, but for
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* the "sake of consistency" it was kept. For certain AP designs, this
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* value is overwritten by the value in the flag "pwrTableOffset" just
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* before writing the pdadc vs pwr into the chip registers.
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*/
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#define AR9300_PWR_TABLE_OFFSET 0
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/* byte addressable */
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#define AR9300_EEPROM_SIZE (16*1024)
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#define AR9300_BASE_ADDR_4K 0xfff
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#define AR9300_BASE_ADDR 0x3ff
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#define AR9300_BASE_ADDR_512 0x1ff
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#define AR9300_OTP_BASE (AR_SREV_9340(ah) ? 0x30000 : 0x14000)
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#define AR9300_OTP_STATUS (AR_SREV_9340(ah) ? 0x30018 : 0x15f18)
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#define AR9300_OTP_STATUS_TYPE 0x7
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#define AR9300_OTP_STATUS_VALID 0x4
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#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
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#define AR9300_OTP_STATUS_SM_BUSY 0x1
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#define AR9300_OTP_READ_DATA (AR_SREV_9340(ah) ? 0x3001c : 0x15f1c)
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enum targetPowerHTRates {
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HT_TARGET_RATE_0_8_16,
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HT_TARGET_RATE_1_3_9_11_17_19,
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HT_TARGET_RATE_4,
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HT_TARGET_RATE_5,
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HT_TARGET_RATE_6,
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HT_TARGET_RATE_7,
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HT_TARGET_RATE_12,
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HT_TARGET_RATE_13,
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HT_TARGET_RATE_14,
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HT_TARGET_RATE_15,
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HT_TARGET_RATE_20,
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HT_TARGET_RATE_21,
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HT_TARGET_RATE_22,
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HT_TARGET_RATE_23
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};
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enum targetPowerLegacyRates {
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LEGACY_TARGET_RATE_6_24,
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LEGACY_TARGET_RATE_36,
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LEGACY_TARGET_RATE_48,
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LEGACY_TARGET_RATE_54
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};
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enum targetPowerCckRates {
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LEGACY_TARGET_RATE_1L_5L,
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LEGACY_TARGET_RATE_5S,
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LEGACY_TARGET_RATE_11L,
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LEGACY_TARGET_RATE_11S
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};
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enum ar9300_Rates {
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ALL_TARGET_LEGACY_6_24,
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ALL_TARGET_LEGACY_36,
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ALL_TARGET_LEGACY_48,
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ALL_TARGET_LEGACY_54,
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ALL_TARGET_LEGACY_1L_5L,
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ALL_TARGET_LEGACY_5S,
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ALL_TARGET_LEGACY_11L,
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ALL_TARGET_LEGACY_11S,
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ALL_TARGET_HT20_0_8_16,
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ALL_TARGET_HT20_1_3_9_11_17_19,
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ALL_TARGET_HT20_4,
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ALL_TARGET_HT20_5,
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ALL_TARGET_HT20_6,
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ALL_TARGET_HT20_7,
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ALL_TARGET_HT20_12,
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ALL_TARGET_HT20_13,
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ALL_TARGET_HT20_14,
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ALL_TARGET_HT20_15,
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ALL_TARGET_HT20_20,
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ALL_TARGET_HT20_21,
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ALL_TARGET_HT20_22,
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ALL_TARGET_HT20_23,
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ALL_TARGET_HT40_0_8_16,
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ALL_TARGET_HT40_1_3_9_11_17_19,
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ALL_TARGET_HT40_4,
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ALL_TARGET_HT40_5,
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ALL_TARGET_HT40_6,
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ALL_TARGET_HT40_7,
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ALL_TARGET_HT40_12,
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ALL_TARGET_HT40_13,
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ALL_TARGET_HT40_14,
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ALL_TARGET_HT40_15,
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ALL_TARGET_HT40_20,
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ALL_TARGET_HT40_21,
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ALL_TARGET_HT40_22,
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ALL_TARGET_HT40_23,
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ar9300RateSize,
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};
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struct eepFlags {
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u8 opFlags;
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u8 eepMisc;
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} __packed;
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enum CompressAlgorithm {
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_CompressNone = 0,
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_CompressLzma,
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_CompressPairs,
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_CompressBlock,
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_Compress4,
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_Compress5,
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_Compress6,
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_Compress7,
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};
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struct ar9300_base_eep_hdr {
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__le16 regDmn[2];
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/* 4 bits tx and 4 bits rx */
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u8 txrxMask;
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struct eepFlags opCapFlags;
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u8 rfSilent;
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u8 blueToothOptions;
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u8 deviceCap;
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/* takes lower byte in eeprom location */
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u8 deviceType;
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/* offset in dB to be added to beginning
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* of pdadc table in calibration
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*/
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int8_t pwrTableOffset;
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u8 params_for_tuning_caps[2];
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/*
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* bit0 - enable tx temp comp
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* bit1 - enable tx volt comp
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* bit2 - enable fastClock - default to 1
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* bit3 - enable doubling - default to 1
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* bit4 - enable internal regulator - default to 1
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*/
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u8 featureEnable;
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/* misc flags: bit0 - turn down drivestrength */
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u8 miscConfiguration;
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u8 eepromWriteEnableGpio;
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u8 wlanDisableGpio;
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u8 wlanLedGpio;
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u8 rxBandSelectGpio;
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u8 txrxgain;
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/* SW controlled internal regulator fields */
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__le32 swreg;
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} __packed;
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struct ar9300_modal_eep_header {
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/* 4 idle, t1, t2, b (4 bits per setting) */
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__le32 antCtrlCommon;
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/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
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__le32 antCtrlCommon2;
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/* 6 idle, t, r, rx1, rx12, b (2 bits each) */
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__le16 antCtrlChain[AR9300_MAX_CHAINS];
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/* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
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u8 xatten1DB[AR9300_MAX_CHAINS];
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/* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
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u8 xatten1Margin[AR9300_MAX_CHAINS];
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int8_t tempSlope;
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int8_t voltSlope;
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/* spur channels in usual fbin coding format */
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u8 spurChans[AR_EEPROM_MODAL_SPURS];
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/* 3 Check if the register is per chain */
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int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
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u8 reserved[11];
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int8_t quick_drop;
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u8 xpaBiasLvl;
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u8 txFrameToDataStart;
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u8 txFrameToPaOn;
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u8 txClip;
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int8_t antennaGain;
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u8 switchSettling;
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int8_t adcDesiredSize;
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u8 txEndToXpaOff;
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u8 txEndToRxOn;
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u8 txFrameToXpaOn;
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u8 thresh62;
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__le32 papdRateMaskHt20;
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__le32 papdRateMaskHt40;
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__le16 switchcomspdt;
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u8 xlna_bias_strength;
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u8 futureModal[7];
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} __packed;
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struct ar9300_cal_data_per_freq_op_loop {
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int8_t refPower;
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/* pdadc voltage at power measurement */
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u8 voltMeas;
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/* pcdac used for power measurement */
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u8 tempMeas;
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/* range is -60 to -127 create a mapping equation 1db resolution */
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int8_t rxNoisefloorCal;
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/*range is same as noisefloor */
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int8_t rxNoisefloorPower;
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/* temp measured when noisefloor cal was performed */
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u8 rxTempMeas;
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} __packed;
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struct cal_tgt_pow_legacy {
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u8 tPow2x[4];
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} __packed;
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struct cal_tgt_pow_ht {
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u8 tPow2x[14];
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} __packed;
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struct cal_ctl_data_2g {
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u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
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} __packed;
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struct cal_ctl_data_5g {
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u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
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} __packed;
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struct ar9300_BaseExtension_1 {
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u8 ant_div_control;
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u8 future[3];
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u8 tempslopextension[8];
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int8_t quick_drop_low;
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int8_t quick_drop_high;
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} __packed;
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struct ar9300_BaseExtension_2 {
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int8_t tempSlopeLow;
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int8_t tempSlopeHigh;
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u8 xatten1DBLow[AR9300_MAX_CHAINS];
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u8 xatten1MarginLow[AR9300_MAX_CHAINS];
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u8 xatten1DBHigh[AR9300_MAX_CHAINS];
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u8 xatten1MarginHigh[AR9300_MAX_CHAINS];
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} __packed;
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struct ar9300_eeprom {
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u8 eepromVersion;
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u8 templateVersion;
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u8 macAddr[6];
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u8 custData[AR9300_CUSTOMER_DATA_SIZE];
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struct ar9300_base_eep_hdr baseEepHeader;
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struct ar9300_modal_eep_header modalHeader2G;
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struct ar9300_BaseExtension_1 base_ext1;
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u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
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struct ar9300_cal_data_per_freq_op_loop
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calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
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u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
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u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
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u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
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u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
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struct cal_tgt_pow_legacy
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calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
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struct cal_tgt_pow_legacy
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calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
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struct cal_tgt_pow_ht
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calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
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struct cal_tgt_pow_ht
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calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
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u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
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u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
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struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
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struct ar9300_modal_eep_header modalHeader5G;
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struct ar9300_BaseExtension_2 base_ext2;
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u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
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struct ar9300_cal_data_per_freq_op_loop
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calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
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u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
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u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
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u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
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struct cal_tgt_pow_legacy
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calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
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struct cal_tgt_pow_ht
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calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
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struct cal_tgt_pow_ht
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calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
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u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
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u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
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struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
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} __packed;
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s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
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s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
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u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);
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unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
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struct ath9k_channel *chan);
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void ar9003_hw_internal_regulator_apply(struct ath_hw *ah);
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#endif
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