Tudor Ambarus 191f5c2ed4 mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes ... SPI memory devices from different manufacturers have widely different configurations for Status, Control and Configuration registers. JEDEC 216C defines a new map for these common register bits and their functions, and describes how the individual bits may be accessed for a specific device. For the JEDEC 216B compliant flashes, we can partially deduce Status and Configuration registers functions by inspecting the 16th DWORD of BFPT. Older flashes that don't declare the SFDP tables (SPANSION FL512SAIFG1 311QQ063 A ©11 SPANSION) let the software decide how to interact with these registers. The commit dcb4b22eea ("spi-nor: s25fl512s supports region locking") uncovered a probe error for s25fl512s, when the Quad Enable bit CR[1] was set to one in the bootloader. When this bit is one, only the Write Status (01h) command with two data byts may be used, the 01h command with one data byte is not recognized and hence the error when trying to clear the block protection bits. Fix the above by using the Write Status (01h) command with two data bytes when the Quad Enable bit is one. Backward compatibility should be fine. The newly introduced spi_nor_spansion_clear_sr_bp() is tightly coupled with the spansion_quad_enable() function. Both assume that the Write Register with 16 bits, together with the Read Configuration Register (35h) instructions are supported. Fixes: dcb4b22eea ("spi-nor: s25fl512s supports region locking") Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Jonas Bonn <jonas@norrbonn.se> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>		2019-06-23 20:03:34 +02:00
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bbm.h	mtd: nand: Cleanup flags and fields for bad block marker position	2019-04-18 08:54:07 +02:00
blktrans.h	mtd_blkdevs: convert to blk-mq	2018-10-16 08:09:58 -06:00
cfi_endian.h
cfi.h	mtd: spi-nor: add macros related to MICRON flash	2018-12-10 21:59:07 +01:00
concat.h
doc2000.h
flashchip.h
ftl.h
gen_probe.h
inftl.h
jedec.h	mtd: rawnand: Move JEDEC code to nand_jedec.c	2018-10-03 11:12:25 +02:00
latch-addr-flash.h
lpc32xx_mlc.h
lpc32xx_slc.h
map.h
mtd.h	Char/Misc driver patches for 4.21-rc1	2018-12-28 20:54:57 -08:00
mtdram.h
nand_bch.h	mtd: nand: Clarify Kconfig entry for software BCH ECC algorithm	2019-04-18 08:54:00 +02:00
nand_ecc.h	mtd: rawnand: Allow selection of ECC byte ordering at runtime	2018-10-03 11:12:25 +02:00
nand-gpio.h
nand.h	mtd: nand: Add a helper to retrieve the number of pages per target	2019-04-08 10:21:09 +02:00
ndfc.h
nftl.h
onenand_regs.h
onenand.h	mtd: onenand: Store bad block marker position in chip struct	2019-04-18 08:54:07 +02:00
onfi.h	mtd: rawnand: Move ONFI code to nand_onfi.c	2018-10-03 11:12:25 +02:00
partitions.h
pfow.h
physmap.h
pismo.h
plat-ram.h
platnand.h	mtd: rawnand: Move platform_nand_xxx definitions out of rawnand.h	2018-10-03 11:12:25 +02:00
qinfo.h
rawnand.h	mtd: nand: Make flags for bad block marker position more granular	2019-04-18 08:54:07 +02:00
sh_flctl.h	mtd: rawnand: sh_flctl: convert to SPDX identifiers	2018-11-13 09:32:04 +01:00
sharpsl.h
spear_smi.h
spi-nor.h	mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes	2019-06-23 20:03:34 +02:00
spinand.h	mtd: spinand: Use the spi-mem dirmap API	2019-03-21 16:44:51 +01:00
super.h
ubi.h
xip.h