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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
514 lines
13 KiB
C
514 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright 2009-2010 Pengutronix
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* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
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*
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* loosely based on an earlier driver that has
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* Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*/
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/core.h>
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#include "mc13xxx.h"
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#define MC13XXX_IRQSTAT0 0
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#define MC13XXX_IRQMASK0 1
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#define MC13XXX_IRQSTAT1 3
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#define MC13XXX_IRQMASK1 4
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#define MC13XXX_REVISION 7
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#define MC13XXX_REVISION_REVMETAL (0x07 << 0)
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#define MC13XXX_REVISION_REVFULL (0x03 << 3)
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#define MC13XXX_REVISION_ICID (0x07 << 6)
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#define MC13XXX_REVISION_FIN (0x03 << 9)
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#define MC13XXX_REVISION_FAB (0x03 << 11)
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#define MC13XXX_REVISION_ICIDCODE (0x3f << 13)
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#define MC34708_REVISION_REVMETAL (0x07 << 0)
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#define MC34708_REVISION_REVFULL (0x07 << 3)
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#define MC34708_REVISION_FIN (0x07 << 6)
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#define MC34708_REVISION_FAB (0x07 << 9)
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#define MC13XXX_PWRCTRL 15
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#define MC13XXX_PWRCTRL_WDIRESET (1 << 12)
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#define MC13XXX_ADC1 44
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#define MC13XXX_ADC1_ADEN (1 << 0)
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#define MC13XXX_ADC1_RAND (1 << 1)
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#define MC13XXX_ADC1_ADSEL (1 << 3)
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#define MC13XXX_ADC1_ASC (1 << 20)
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#define MC13XXX_ADC1_ADTRIGIGN (1 << 21)
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#define MC13XXX_ADC2 45
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void mc13xxx_lock(struct mc13xxx *mc13xxx)
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{
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if (!mutex_trylock(&mc13xxx->lock)) {
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dev_dbg(mc13xxx->dev, "wait for %s from %ps\n",
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__func__, __builtin_return_address(0));
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mutex_lock(&mc13xxx->lock);
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}
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dev_dbg(mc13xxx->dev, "%s from %ps\n",
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__func__, __builtin_return_address(0));
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}
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EXPORT_SYMBOL(mc13xxx_lock);
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void mc13xxx_unlock(struct mc13xxx *mc13xxx)
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{
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dev_dbg(mc13xxx->dev, "%s from %ps\n",
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__func__, __builtin_return_address(0));
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mutex_unlock(&mc13xxx->lock);
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}
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EXPORT_SYMBOL(mc13xxx_unlock);
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int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
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{
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int ret;
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ret = regmap_read(mc13xxx->regmap, offset, val);
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dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
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return ret;
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}
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EXPORT_SYMBOL(mc13xxx_reg_read);
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int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
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{
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dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val);
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if (val >= BIT(24))
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return -EINVAL;
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return regmap_write(mc13xxx->regmap, offset, val);
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}
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EXPORT_SYMBOL(mc13xxx_reg_write);
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int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
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u32 mask, u32 val)
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{
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BUG_ON(val & ~mask);
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dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x (mask: 0x%06x)\n",
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offset, val, mask);
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return regmap_update_bits(mc13xxx->regmap, offset, mask, val);
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}
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EXPORT_SYMBOL(mc13xxx_reg_rmw);
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int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
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{
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int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
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disable_irq_nosync(virq);
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return 0;
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}
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EXPORT_SYMBOL(mc13xxx_irq_mask);
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int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
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{
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int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
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enable_irq(virq);
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return 0;
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}
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EXPORT_SYMBOL(mc13xxx_irq_unmask);
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int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
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int *enabled, int *pending)
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{
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int ret;
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unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
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unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
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u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
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if (irq < 0 || irq >= ARRAY_SIZE(mc13xxx->irqs))
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return -EINVAL;
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if (enabled) {
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u32 mask;
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ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
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if (ret)
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return ret;
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*enabled = mask & irqbit;
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}
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if (pending) {
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u32 stat;
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ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
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if (ret)
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return ret;
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*pending = stat & irqbit;
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}
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return 0;
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}
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EXPORT_SYMBOL(mc13xxx_irq_status);
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int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
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irq_handler_t handler, const char *name, void *dev)
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{
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int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
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return devm_request_threaded_irq(mc13xxx->dev, virq, NULL, handler,
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IRQF_ONESHOT, name, dev);
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}
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EXPORT_SYMBOL(mc13xxx_irq_request);
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int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev)
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{
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int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
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devm_free_irq(mc13xxx->dev, virq, dev);
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return 0;
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}
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EXPORT_SYMBOL(mc13xxx_irq_free);
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#define maskval(reg, mask) (((reg) & (mask)) >> __ffs(mask))
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static void mc13xxx_print_revision(struct mc13xxx *mc13xxx, u32 revision)
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{
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dev_info(mc13xxx->dev, "%s: rev: %d.%d, "
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"fin: %d, fab: %d, icid: %d/%d\n",
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mc13xxx->variant->name,
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maskval(revision, MC13XXX_REVISION_REVFULL),
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maskval(revision, MC13XXX_REVISION_REVMETAL),
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maskval(revision, MC13XXX_REVISION_FIN),
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maskval(revision, MC13XXX_REVISION_FAB),
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maskval(revision, MC13XXX_REVISION_ICID),
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maskval(revision, MC13XXX_REVISION_ICIDCODE));
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}
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static void mc34708_print_revision(struct mc13xxx *mc13xxx, u32 revision)
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{
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dev_info(mc13xxx->dev, "%s: rev %d.%d, fin: %d, fab: %d\n",
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mc13xxx->variant->name,
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maskval(revision, MC34708_REVISION_REVFULL),
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maskval(revision, MC34708_REVISION_REVMETAL),
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maskval(revision, MC34708_REVISION_FIN),
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maskval(revision, MC34708_REVISION_FAB));
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}
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/* These are only exported for mc13xxx-i2c and mc13xxx-spi */
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struct mc13xxx_variant mc13xxx_variant_mc13783 = {
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.name = "mc13783",
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.print_revision = mc13xxx_print_revision,
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};
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EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13783);
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struct mc13xxx_variant mc13xxx_variant_mc13892 = {
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.name = "mc13892",
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.print_revision = mc13xxx_print_revision,
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};
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EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13892);
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struct mc13xxx_variant mc13xxx_variant_mc34708 = {
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.name = "mc34708",
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.print_revision = mc34708_print_revision,
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};
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EXPORT_SYMBOL_GPL(mc13xxx_variant_mc34708);
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static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
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{
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return mc13xxx->variant->name;
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}
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int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
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{
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return mc13xxx->flags;
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}
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EXPORT_SYMBOL(mc13xxx_get_flags);
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#define MC13XXX_ADC1_CHAN0_SHIFT 5
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#define MC13XXX_ADC1_CHAN1_SHIFT 8
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#define MC13783_ADC1_ATO_SHIFT 11
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#define MC13783_ADC1_ATOX (1 << 19)
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struct mc13xxx_adcdone_data {
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struct mc13xxx *mc13xxx;
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struct completion done;
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};
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static irqreturn_t mc13xxx_handler_adcdone(int irq, void *data)
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{
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struct mc13xxx_adcdone_data *adcdone_data = data;
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complete_all(&adcdone_data->done);
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return IRQ_HANDLED;
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}
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#define MC13XXX_ADC_WORKING (1 << 0)
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int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
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unsigned int channel, u8 ato, bool atox,
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unsigned int *sample)
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{
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u32 adc0, adc1, old_adc0;
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int i, ret;
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struct mc13xxx_adcdone_data adcdone_data = {
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.mc13xxx = mc13xxx,
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};
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init_completion(&adcdone_data.done);
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dev_dbg(mc13xxx->dev, "%s\n", __func__);
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mc13xxx_lock(mc13xxx);
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if (mc13xxx->adcflags & MC13XXX_ADC_WORKING) {
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ret = -EBUSY;
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goto out;
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}
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mc13xxx->adcflags |= MC13XXX_ADC_WORKING;
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ret = mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0);
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if (ret)
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goto out;
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adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2 |
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MC13XXX_ADC0_CHRGRAWDIV;
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adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC;
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/*
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* Channels mapped through ADIN7:
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* 7 - General purpose ADIN7
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* 16 - UID
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* 17 - Die temperature
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*/
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if (channel > 7 && channel < 16) {
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adc1 |= MC13XXX_ADC1_ADSEL;
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} else if (channel == 16) {
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adc0 |= MC13XXX_ADC0_ADIN7SEL_UID;
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channel = 7;
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} else if (channel == 17) {
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adc0 |= MC13XXX_ADC0_ADIN7SEL_DIE;
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channel = 7;
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}
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switch (mode) {
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case MC13XXX_ADC_MODE_TS:
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adc0 |= MC13XXX_ADC0_ADREFEN | MC13XXX_ADC0_TSMOD0 |
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MC13XXX_ADC0_TSMOD1;
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adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
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break;
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case MC13XXX_ADC_MODE_SINGLE_CHAN:
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adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
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adc1 |= (channel & 0x7) << MC13XXX_ADC1_CHAN0_SHIFT;
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adc1 |= MC13XXX_ADC1_RAND;
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break;
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case MC13XXX_ADC_MODE_MULT_CHAN:
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adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
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adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
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break;
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default:
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mc13xxx_unlock(mc13xxx);
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return -EINVAL;
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}
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adc1 |= ato << MC13783_ADC1_ATO_SHIFT;
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if (atox)
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adc1 |= MC13783_ADC1_ATOX;
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dev_dbg(mc13xxx->dev, "%s: request irq\n", __func__);
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mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
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mc13xxx_handler_adcdone, __func__, &adcdone_data);
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mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, adc0);
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mc13xxx_reg_write(mc13xxx, MC13XXX_ADC1, adc1);
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mc13xxx_unlock(mc13xxx);
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ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
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if (!ret)
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ret = -ETIMEDOUT;
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mc13xxx_lock(mc13xxx);
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mc13xxx_irq_free(mc13xxx, MC13XXX_IRQ_ADCDONE, &adcdone_data);
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if (ret > 0)
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for (i = 0; i < 4; ++i) {
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ret = mc13xxx_reg_read(mc13xxx,
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MC13XXX_ADC2, &sample[i]);
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if (ret)
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break;
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}
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if (mode == MC13XXX_ADC_MODE_TS)
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/* restore TSMOD */
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mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, old_adc0);
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mc13xxx->adcflags &= ~MC13XXX_ADC_WORKING;
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out:
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mc13xxx_unlock(mc13xxx);
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return ret;
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}
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EXPORT_SYMBOL_GPL(mc13xxx_adc_do_conversion);
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static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
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const char *format, void *pdata, size_t pdata_size)
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{
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char buf[30];
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const char *name = mc13xxx_get_chipname(mc13xxx);
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struct mfd_cell cell = {
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.platform_data = pdata,
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.pdata_size = pdata_size,
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};
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/* there is no asnprintf in the kernel :-( */
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if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
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return -E2BIG;
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cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
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if (!cell.name)
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return -ENOMEM;
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return mfd_add_devices(mc13xxx->dev, -1, &cell, 1, NULL, 0,
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regmap_irq_get_domain(mc13xxx->irq_data));
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}
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static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
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{
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return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
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}
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#ifdef CONFIG_OF
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static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
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{
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struct device_node *np = mc13xxx->dev->of_node;
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if (!np)
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return -ENODEV;
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if (of_property_read_bool(np, "fsl,mc13xxx-uses-adc"))
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mc13xxx->flags |= MC13XXX_USE_ADC;
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if (of_property_read_bool(np, "fsl,mc13xxx-uses-codec"))
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mc13xxx->flags |= MC13XXX_USE_CODEC;
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if (of_property_read_bool(np, "fsl,mc13xxx-uses-rtc"))
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mc13xxx->flags |= MC13XXX_USE_RTC;
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if (of_property_read_bool(np, "fsl,mc13xxx-uses-touch"))
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mc13xxx->flags |= MC13XXX_USE_TOUCHSCREEN;
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return 0;
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}
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#else
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static inline int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
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{
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return -ENODEV;
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}
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#endif
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int mc13xxx_common_init(struct device *dev)
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{
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struct mc13xxx_platform_data *pdata = dev_get_platdata(dev);
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struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
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u32 revision;
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int i, ret;
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mc13xxx->dev = dev;
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ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
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if (ret)
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return ret;
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mc13xxx->variant->print_revision(mc13xxx, revision);
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ret = mc13xxx_reg_rmw(mc13xxx, MC13XXX_PWRCTRL,
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MC13XXX_PWRCTRL_WDIRESET, MC13XXX_PWRCTRL_WDIRESET);
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if (ret)
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return ret;
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for (i = 0; i < ARRAY_SIZE(mc13xxx->irqs); i++) {
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mc13xxx->irqs[i].reg_offset = i / MC13XXX_IRQ_PER_REG;
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mc13xxx->irqs[i].mask = BIT(i % MC13XXX_IRQ_PER_REG);
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}
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mc13xxx->irq_chip.name = dev_name(dev);
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mc13xxx->irq_chip.status_base = MC13XXX_IRQSTAT0;
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mc13xxx->irq_chip.mask_base = MC13XXX_IRQMASK0;
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mc13xxx->irq_chip.ack_base = MC13XXX_IRQSTAT0;
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mc13xxx->irq_chip.irq_reg_stride = MC13XXX_IRQSTAT1 - MC13XXX_IRQSTAT0;
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mc13xxx->irq_chip.init_ack_masked = true;
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mc13xxx->irq_chip.use_ack = true;
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mc13xxx->irq_chip.num_regs = MC13XXX_IRQ_REG_CNT;
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mc13xxx->irq_chip.irqs = mc13xxx->irqs;
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mc13xxx->irq_chip.num_irqs = ARRAY_SIZE(mc13xxx->irqs);
|
|
|
|
ret = regmap_add_irq_chip(mc13xxx->regmap, mc13xxx->irq, IRQF_ONESHOT,
|
|
0, &mc13xxx->irq_chip, &mc13xxx->irq_data);
|
|
if (ret)
|
|
return ret;
|
|
|
|
mutex_init(&mc13xxx->lock);
|
|
|
|
if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata)
|
|
mc13xxx->flags = pdata->flags;
|
|
|
|
if (pdata) {
|
|
mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
|
|
&pdata->regulators, sizeof(pdata->regulators));
|
|
mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
|
|
pdata->leds, sizeof(*pdata->leds));
|
|
mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton",
|
|
pdata->buttons, sizeof(*pdata->buttons));
|
|
if (mc13xxx->flags & MC13XXX_USE_CODEC)
|
|
mc13xxx_add_subdevice_pdata(mc13xxx, "%s-codec",
|
|
pdata->codec, sizeof(*pdata->codec));
|
|
if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
|
|
mc13xxx_add_subdevice_pdata(mc13xxx, "%s-ts",
|
|
&pdata->touch, sizeof(pdata->touch));
|
|
} else {
|
|
mc13xxx_add_subdevice(mc13xxx, "%s-regulator");
|
|
mc13xxx_add_subdevice(mc13xxx, "%s-led");
|
|
mc13xxx_add_subdevice(mc13xxx, "%s-pwrbutton");
|
|
if (mc13xxx->flags & MC13XXX_USE_CODEC)
|
|
mc13xxx_add_subdevice(mc13xxx, "%s-codec");
|
|
if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
|
|
mc13xxx_add_subdevice(mc13xxx, "%s-ts");
|
|
}
|
|
|
|
if (mc13xxx->flags & MC13XXX_USE_ADC)
|
|
mc13xxx_add_subdevice(mc13xxx, "%s-adc");
|
|
|
|
if (mc13xxx->flags & MC13XXX_USE_RTC)
|
|
mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(mc13xxx_common_init);
|
|
|
|
int mc13xxx_common_exit(struct device *dev)
|
|
{
|
|
struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
|
|
|
|
mfd_remove_devices(dev);
|
|
regmap_del_irq_chip(mc13xxx->irq, mc13xxx->irq_data);
|
|
mutex_destroy(&mc13xxx->lock);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(mc13xxx_common_exit);
|
|
|
|
MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
|
|
MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
|
|
MODULE_LICENSE("GPL v2");
|