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b0200065cd
This patch corrects the SPDX License Identifier style in header file related to Crypto Drivers for Hisilicon SEC Engine in Hip06 and Hip07. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used) Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46 Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
429 lines
12 KiB
C
429 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2016-2017 Hisilicon Limited. */
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#ifndef _SEC_DRV_H_
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#define _SEC_DRV_H_
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#include <crypto/algapi.h>
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#include <linux/kfifo.h>
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#define SEC_MAX_SGE_NUM 64
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#define SEC_HW_RING_NUM 3
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#define SEC_CMD_RING 0
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#define SEC_OUTORDER_RING 1
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#define SEC_DBG_RING 2
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/* A reasonable length to balance memory use against flexibility */
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#define SEC_QUEUE_LEN 512
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#define SEC_MAX_SGE_NUM 64
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struct sec_bd_info {
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#define SEC_BD_W0_T_LEN_M GENMASK(4, 0)
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#define SEC_BD_W0_T_LEN_S 0
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#define SEC_BD_W0_C_WIDTH_M GENMASK(6, 5)
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#define SEC_BD_W0_C_WIDTH_S 5
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#define SEC_C_WIDTH_AES_128BIT 0
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#define SEC_C_WIDTH_AES_8BIT 1
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#define SEC_C_WIDTH_AES_1BIT 2
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#define SEC_C_WIDTH_DES_64BIT 0
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#define SEC_C_WIDTH_DES_8BIT 1
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#define SEC_C_WIDTH_DES_1BIT 2
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#define SEC_BD_W0_C_MODE_M GENMASK(9, 7)
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#define SEC_BD_W0_C_MODE_S 7
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#define SEC_C_MODE_ECB 0
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#define SEC_C_MODE_CBC 1
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#define SEC_C_MODE_CTR 4
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#define SEC_C_MODE_CCM 5
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#define SEC_C_MODE_GCM 6
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#define SEC_C_MODE_XTS 7
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#define SEC_BD_W0_SEQ BIT(10)
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#define SEC_BD_W0_DE BIT(11)
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#define SEC_BD_W0_DAT_SKIP_M GENMASK(13, 12)
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#define SEC_BD_W0_DAT_SKIP_S 12
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#define SEC_BD_W0_C_GRAN_SIZE_19_16_M GENMASK(17, 14)
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#define SEC_BD_W0_C_GRAN_SIZE_19_16_S 14
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#define SEC_BD_W0_CIPHER_M GENMASK(19, 18)
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#define SEC_BD_W0_CIPHER_S 18
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#define SEC_CIPHER_NULL 0
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#define SEC_CIPHER_ENCRYPT 1
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#define SEC_CIPHER_DECRYPT 2
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#define SEC_BD_W0_AUTH_M GENMASK(21, 20)
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#define SEC_BD_W0_AUTH_S 20
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#define SEC_AUTH_NULL 0
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#define SEC_AUTH_MAC 1
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#define SEC_AUTH_VERIF 2
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#define SEC_BD_W0_AI_GEN BIT(22)
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#define SEC_BD_W0_CI_GEN BIT(23)
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#define SEC_BD_W0_NO_HPAD BIT(24)
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#define SEC_BD_W0_HM_M GENMASK(26, 25)
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#define SEC_BD_W0_HM_S 25
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#define SEC_BD_W0_ICV_OR_SKEY_EN_M GENMASK(28, 27)
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#define SEC_BD_W0_ICV_OR_SKEY_EN_S 27
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/* Multi purpose field - gran size bits for send, flag for recv */
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#define SEC_BD_W0_FLAG_M GENMASK(30, 29)
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#define SEC_BD_W0_C_GRAN_SIZE_21_20_M GENMASK(30, 29)
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#define SEC_BD_W0_FLAG_S 29
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#define SEC_BD_W0_C_GRAN_SIZE_21_20_S 29
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#define SEC_BD_W0_DONE BIT(31)
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u32 w0;
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#define SEC_BD_W1_AUTH_GRAN_SIZE_M GENMASK(21, 0)
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#define SEC_BD_W1_AUTH_GRAN_SIZE_S 0
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#define SEC_BD_W1_M_KEY_EN BIT(22)
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#define SEC_BD_W1_BD_INVALID BIT(23)
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#define SEC_BD_W1_ADDR_TYPE BIT(24)
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#define SEC_BD_W1_A_ALG_M GENMASK(28, 25)
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#define SEC_BD_W1_A_ALG_S 25
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#define SEC_A_ALG_SHA1 0
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#define SEC_A_ALG_SHA256 1
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#define SEC_A_ALG_MD5 2
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#define SEC_A_ALG_SHA224 3
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#define SEC_A_ALG_HMAC_SHA1 8
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#define SEC_A_ALG_HMAC_SHA224 10
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#define SEC_A_ALG_HMAC_SHA256 11
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#define SEC_A_ALG_HMAC_MD5 12
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#define SEC_A_ALG_AES_XCBC 13
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#define SEC_A_ALG_AES_CMAC 14
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#define SEC_BD_W1_C_ALG_M GENMASK(31, 29)
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#define SEC_BD_W1_C_ALG_S 29
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#define SEC_C_ALG_DES 0
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#define SEC_C_ALG_3DES 1
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#define SEC_C_ALG_AES 2
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u32 w1;
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#define SEC_BD_W2_C_GRAN_SIZE_15_0_M GENMASK(15, 0)
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#define SEC_BD_W2_C_GRAN_SIZE_15_0_S 0
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#define SEC_BD_W2_GRAN_NUM_M GENMASK(31, 16)
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#define SEC_BD_W2_GRAN_NUM_S 16
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u32 w2;
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#define SEC_BD_W3_AUTH_LEN_OFFSET_M GENMASK(9, 0)
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#define SEC_BD_W3_AUTH_LEN_OFFSET_S 0
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#define SEC_BD_W3_CIPHER_LEN_OFFSET_M GENMASK(19, 10)
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#define SEC_BD_W3_CIPHER_LEN_OFFSET_S 10
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#define SEC_BD_W3_MAC_LEN_M GENMASK(24, 20)
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#define SEC_BD_W3_MAC_LEN_S 20
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#define SEC_BD_W3_A_KEY_LEN_M GENMASK(29, 25)
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#define SEC_BD_W3_A_KEY_LEN_S 25
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#define SEC_BD_W3_C_KEY_LEN_M GENMASK(31, 30)
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#define SEC_BD_W3_C_KEY_LEN_S 30
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#define SEC_KEY_LEN_AES_128 0
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#define SEC_KEY_LEN_AES_192 1
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#define SEC_KEY_LEN_AES_256 2
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#define SEC_KEY_LEN_DES 1
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#define SEC_KEY_LEN_3DES_3_KEY 1
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#define SEC_KEY_LEN_3DES_2_KEY 3
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u32 w3;
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/* W4,5 */
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union {
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u32 authkey_addr_lo;
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u32 authiv_addr_lo;
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};
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union {
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u32 authkey_addr_hi;
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u32 authiv_addr_hi;
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};
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/* W6,7 */
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u32 cipher_key_addr_lo;
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u32 cipher_key_addr_hi;
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/* W8,9 */
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u32 cipher_iv_addr_lo;
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u32 cipher_iv_addr_hi;
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/* W10,11 */
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u32 data_addr_lo;
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u32 data_addr_hi;
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/* W12,13 */
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u32 mac_addr_lo;
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u32 mac_addr_hi;
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/* W14,15 */
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u32 cipher_destin_addr_lo;
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u32 cipher_destin_addr_hi;
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};
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enum sec_mem_region {
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SEC_COMMON = 0,
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SEC_SAA,
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SEC_NUM_ADDR_REGIONS
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};
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#define SEC_NAME_SIZE 64
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#define SEC_Q_NUM 16
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/**
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* struct sec_queue_ring_cmd - store information about a SEC HW cmd ring
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* @used: Local counter used to cheaply establish if the ring is empty.
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* @lock: Protect against simultaneous adjusting of the read and write pointers.
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* @vaddr: Virtual address for the ram pages used for the ring.
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* @paddr: Physical address of the dma mapped region of ram used for the ring.
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* @callback: Callback function called on a ring element completing.
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*/
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struct sec_queue_ring_cmd {
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atomic_t used;
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struct mutex lock;
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struct sec_bd_info *vaddr;
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dma_addr_t paddr;
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void (*callback)(struct sec_bd_info *resp, void *ctx);
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};
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struct sec_debug_bd_info;
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struct sec_queue_ring_db {
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struct sec_debug_bd_info *vaddr;
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dma_addr_t paddr;
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};
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struct sec_out_bd_info;
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struct sec_queue_ring_cq {
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struct sec_out_bd_info *vaddr;
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dma_addr_t paddr;
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};
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struct sec_dev_info;
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enum sec_cipher_alg {
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SEC_C_DES_ECB_64,
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SEC_C_DES_CBC_64,
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SEC_C_3DES_ECB_192_3KEY,
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SEC_C_3DES_ECB_192_2KEY,
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SEC_C_3DES_CBC_192_3KEY,
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SEC_C_3DES_CBC_192_2KEY,
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SEC_C_AES_ECB_128,
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SEC_C_AES_ECB_192,
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SEC_C_AES_ECB_256,
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SEC_C_AES_CBC_128,
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SEC_C_AES_CBC_192,
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SEC_C_AES_CBC_256,
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SEC_C_AES_CTR_128,
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SEC_C_AES_CTR_192,
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SEC_C_AES_CTR_256,
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SEC_C_AES_XTS_128,
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SEC_C_AES_XTS_256,
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SEC_C_NULL,
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};
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/**
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* struct sec_alg_tfm_ctx - hardware specific tranformation context
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* @cipher_alg: Cipher algorithm enabled include encryption mode.
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* @key: Key storage if required.
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* @pkey: DMA address for the key storage.
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* @req_template: Request template to save time on setup.
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* @queue: The hardware queue associated with this tfm context.
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* @lock: Protect key and pkey to ensure they are consistent
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* @auth_buf: Current context buffer for auth operations.
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* @backlog: The backlog queue used for cases where our buffers aren't
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* large enough.
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*/
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struct sec_alg_tfm_ctx {
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enum sec_cipher_alg cipher_alg;
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u8 *key;
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dma_addr_t pkey;
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struct sec_bd_info req_template;
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struct sec_queue *queue;
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struct mutex lock;
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u8 *auth_buf;
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struct list_head backlog;
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};
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/**
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* struct sec_request - data associate with a single crypto request
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* @elements: List of subparts of this request (hardware size restriction)
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* @num_elements: The number of subparts (used as an optimization)
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* @lock: Protect elements of this structure against concurrent change.
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* @tfm_ctx: hardware specific context.
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* @len_in: length of in sgl from upper layers
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* @len_out: length of out sgl from upper layers
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* @dma_iv: initialization vector - phsyical address
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* @err: store used to track errors across subelements of this request.
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* @req_base: pointer to base element of associate crypto context.
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* This is needed to allow shared handling skcipher, ahash etc.
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* @cb: completion callback.
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* @backlog_head: list head to allow backlog maintenance.
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*
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* The hardware is limited in the maximum size of data that it can
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* process from a single BD. Typically this is fairly large (32MB)
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* but still requires the complexity of splitting the incoming
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* skreq up into a number of elements complete with appropriate
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* iv chaining.
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*/
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struct sec_request {
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struct list_head elements;
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int num_elements;
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struct mutex lock;
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struct sec_alg_tfm_ctx *tfm_ctx;
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int len_in;
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int len_out;
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dma_addr_t dma_iv;
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int err;
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struct crypto_async_request *req_base;
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void (*cb)(struct sec_bd_info *resp, struct crypto_async_request *req);
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struct list_head backlog_head;
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};
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/**
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* struct sec_request_el - A subpart of a request.
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* @head: allow us to attach this to the list in the sec_request
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* @req: hardware block descriptor corresponding to this request subpart
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* @in: hardware sgl for input - virtual address
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* @dma_in: hardware sgl for input - physical address
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* @sgl_in: scatterlist for this request subpart
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* @out: hardware sgl for output - virtual address
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* @dma_out: hardware sgl for output - physical address
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* @sgl_out: scatterlist for this request subpart
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* @sec_req: The request which this subpart forms a part of
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* @el_length: Number of bytes in this subpart. Needed to locate
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* last ivsize chunk for iv chaining.
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*/
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struct sec_request_el {
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struct list_head head;
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struct sec_bd_info req;
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struct sec_hw_sgl *in;
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dma_addr_t dma_in;
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struct scatterlist *sgl_in;
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struct sec_hw_sgl *out;
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dma_addr_t dma_out;
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struct scatterlist *sgl_out;
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struct sec_request *sec_req;
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size_t el_length;
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};
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/**
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* struct sec_queue - All the information about a HW queue
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* @dev_info: The parent SEC device to which this queue belongs.
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* @task_irq: Completion interrupt for the queue.
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* @name: Human readable queue description also used as irq name.
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* @ring: The several HW rings associated with one queue.
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* @regs: The iomapped device registers
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* @queue_id: Index of the queue used for naming and resource selection.
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* @in_use: Flag to say if the queue is in use.
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* @expected: The next expected element to finish assuming we were in order.
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* @uprocessed: A bitmap to track which OoO elements are done but not handled.
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* @softqueue: A software queue used when chaining requirements prevent direct
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* use of the hardware queues.
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* @havesoftqueue: A flag to say we have a queues - as we may need one for the
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* current mode.
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* @queuelock: Protect the soft queue from concurrent changes to avoid some
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* potential loss of data races.
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* @shadow: Pointers back to the shadow copy of the hardware ring element
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* need because we can't store any context reference in the bd element.
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*/
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struct sec_queue {
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struct sec_dev_info *dev_info;
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int task_irq;
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char name[SEC_NAME_SIZE];
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struct sec_queue_ring_cmd ring_cmd;
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struct sec_queue_ring_cq ring_cq;
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struct sec_queue_ring_db ring_db;
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void __iomem *regs;
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u32 queue_id;
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bool in_use;
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int expected;
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DECLARE_BITMAP(unprocessed, SEC_QUEUE_LEN);
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DECLARE_KFIFO_PTR(softqueue, typeof(struct sec_request_el *));
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bool havesoftqueue;
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struct mutex queuelock;
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void *shadow[SEC_QUEUE_LEN];
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};
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/**
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* struct sec_hw_sge: Track each of the 64 element SEC HW SGL entries
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* @buf: The IOV dma address for this entry.
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* @len: Length of this IOV.
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* @pad: Reserved space.
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*/
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struct sec_hw_sge {
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dma_addr_t buf;
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unsigned int len;
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unsigned int pad;
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};
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/**
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* struct sec_hw_sgl: One hardware SGL entry.
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* @next_sgl: The next entry if we need to chain dma address. Null if last.
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* @entry_sum_in_chain: The full count of SGEs - only matters for first SGL.
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* @entry_sum_in_sgl: The number of SGEs in this SGL element.
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* @flag: Unused in skciphers.
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* @serial_num: Unsued in skciphers.
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* @cpuid: Currently unused.
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* @data_bytes_in_sgl: Count of bytes from all SGEs in this SGL.
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* @next: Virtual address used to stash the next sgl - useful in completion.
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* @reserved: A reserved field not currently used.
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* @sge_entries: The (up to) 64 Scatter Gather Entries, representing IOVs.
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* @node: Currently unused.
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*/
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struct sec_hw_sgl {
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dma_addr_t next_sgl;
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u16 entry_sum_in_chain;
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u16 entry_sum_in_sgl;
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u32 flag;
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u64 serial_num;
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u32 cpuid;
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u32 data_bytes_in_sgl;
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struct sec_hw_sgl *next;
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u64 reserved;
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struct sec_hw_sge sge_entries[SEC_MAX_SGE_NUM];
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u8 node[16];
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};
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struct dma_pool;
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/**
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* struct sec_dev_info: The full SEC unit comprising queues and processors.
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* @sec_id: Index used to track which SEC this is when more than one is present.
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* @num_saas: The number of backed processors enabled.
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* @regs: iomapped register regions shared by whole SEC unit.
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* @dev_lock: Protects concurrent queue allocation / freeing for the SEC.
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* @queues: The 16 queues that this SEC instance provides.
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* @dev: Device pointer.
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* @hw_sgl_pool: DMA pool used to mimise mapping for the scatter gather lists.
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*/
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struct sec_dev_info {
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int sec_id;
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int num_saas;
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void __iomem *regs[SEC_NUM_ADDR_REGIONS];
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struct mutex dev_lock;
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int queues_in_use;
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struct sec_queue queues[SEC_Q_NUM];
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struct device *dev;
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struct dma_pool *hw_sgl_pool;
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};
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int sec_queue_send(struct sec_queue *queue, struct sec_bd_info *msg, void *ctx);
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bool sec_queue_can_enqueue(struct sec_queue *queue, int num);
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int sec_queue_stop_release(struct sec_queue *queue);
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struct sec_queue *sec_queue_alloc_start_safe(void);
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bool sec_queue_empty(struct sec_queue *queue);
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/* Algorithm specific elements from sec_algs.c */
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void sec_alg_callback(struct sec_bd_info *resp, void *ctx);
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int sec_algs_register(void);
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void sec_algs_unregister(void);
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#endif /* _SEC_DRV_H_ */
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